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TAPR M-51 Operation Manual Download Page 8

M-51 for TUC52, Issue 1.0

 Page 8 

January 21, 1998

File:  m51-i1.doc

m51-> sx b000   {rtn}
xB000: 00       {sp}
xB001: 20 30    {sp}
xB003: 40       {rtn}
m51-> dx f000   {rtn}
xB000:  00 30 40 00  00 00 00 00  00 00 00 00  00 00 00 00  .0@..............
m51->

2.5.1

 

ZNEXT (Z)

The ZNEXT command works exactly like the NEXT command except that when a CALL instruction is
found, the monitor will not step through the subroutine.  It will break at the location the subroutine should
return to.

Be sure to review the section on "Cautions with GO Breakpoints and NEXT" This is important information.

2.6

 

T

EST 

C

OMMANDS IN 

D

ETAIL

This section outlines each test command in more detail.   Test commands are used to exercise various
hardware elements and are machine specific.  These are not expected to be used to debug user’s firmware
and therefor are not restricted from using  Internal Data Memory (IDM) within the 8051 CPU.

2.6.1

 

Test External Data Memory (TX)

The TX command is used to test some contiguous area of External Data Memory.  This is usually the system
RAM.  The test makes use of the standard WRITE, READ, WRITE command with walking 1s and walking
0s that usually picks up crossed (or heavily capacitivly coupled) address and/or data leads.

An example would be:

m51-> tx 0 1000    {rtn}
TR: Write, Read, Write Test....
TR: Loading initial value, 00
TR: Walking ones, 01 02 04 08 10 20 40 80
TR: Loading initial value, FF
TR: Walking zeros, FE FD FB F7 EF DF BF 7F
TR: Random data test...
TR: Test OK!
m51->

3.

 

 MEMORY AND PORT MAPPING

The m-51 monitor, as configured for TUC-52, requires that the monitor ROM start at 0H.  For TUC-52, this
ROM function is provided by the 27c256 installed at IC4.  This ROM must output data to the bus when
PSEN* is active.  PSEN* can be OR-ed with RD* before going to the ROM OE* signal but this isn't a must.

RAM must exist from EF00H to EFFFH and must be double mapped as code and data space (i.e., TUC-52
must OR the PSEN* and RD* signals from the 8032 and connect the output of the OR gate to the RD* input
on the RAM).  On TUC-52 this RAM is function is provided by the 43256 installed at IC6.  When user’s
programs are executed from RAM, that RAM device must be double mapped as program and data space
(i.e., you must OR the PSEN* and RD* signals from the 8032 and connect the output of the OR gate to the
RAM’s OE* input).  On TUC-52 with the shunt settings shown below, the RAM at IC6 will be accessed
from 08000H to 0EFFFH.  The user should stay out of locations 0EF00 to 0EFCF which are used for
monitor functions.

Summary of Contents for M-51

Page 1: ...from double mapped program and data RAM memory This manual describes how to use the monitor what s needed for hardware and different options for recovering the lost P0 and P2 ports which are not available for I O since they are used to create the address and data bus As with all instruction manuals there may be some errors or sections that do not provide satisfactory explanations If you find error...

Page 2: ... a summary for each command The next section provides the details of each command Table 1 Command Summary Command Description Usage BLAST FROM Blast from XDM BF adr data BLAST TO Blast to XDM BT adr data CHECK PROG MEM Checksum of PM CP first last CHECK XDATA Checksum of XDM CX first last DISPLAY PGM Display Program Memory DP first last DISPLAY XDM Display External Data Memory DX first last DISPLA...

Page 3: ...d is followed by two arguments CHECKSUM calculates a 16 bit sum checksum from arg0 to arg1 inclusive and prints the sum on the console Use CP first last for Program Memory and CX first last for XDM An example would be m51 cp 1000 1fff rtn Checksum 14DE m51 2 3 3 DISPLAY DP DX DI DS The DISPLAY is used to show the data at multiple consecutive locations of PM XDM IDM or SFRs Use DP for PM DX for XDM...

Page 4: ...egister incl reg bank XK display and allow changes of just the current reg bank within PSW XRn display and allow changes of Rn of the selected register bank n 0 1 7 XD display and allow changes of the DPTR register 16 bits XB display and allow changes of the B register XS display and allow changes of the SP register XP display and allow changes of the PCTR register 16 bits Some examples would be m...

Page 5: ...or and the monitor will return the original user s data to the breakpoint address The GO command restores all user registers before going to the user program and it saves all user registers following a break point Be sure to review the section near the end of this document titled Cautions with GO Breakpoints NEXT and ZNEXT Commands This is important information 2 3 7 HELP H The HELP command will p...

Page 6: ...register The 8051 will execute one instruction and then go on to the following instruction where it will then encounter the previously placed monitor trap instruction This instruction will transfer execution back to the monitor which will 1 swap the trap instruction with the user s original instruction at the trap address 2 save the user s registers 3 print the user s registers to the terminal and...

Page 7: ...mory space The RXINTEL command may be followed by an optional offset argument The offset value is added to the address contained in each record of the HEX code The result of the addition points to where the data portion of the record will be stored in XDM If the offset is omitted it is assumed to be zero When a record is correctly received a dot will be printed on the console When the end of file ...

Page 8: ...or heavily capacitivly coupled address and or data leads An example would be m51 tx 0 1000 rtn TR Write Read Write Test TR Loading initial value 00 TR Walking ones 01 02 04 08 10 20 40 80 TR Loading initial value FF TR Walking zeros FE FD FB F7 EF DF BF 7F TR Random data test TR Test OK m51 3 MEMORY AND PORT MAPPING The m 51 monitor as configured for TUC 52 requires that the monitor ROM start at 0...

Page 9: ...and P3 7 are lost to RD and WR signals Ports 0 and 2 can be recovered by 8255 I O ports to some extent If possible assign those I Os that need to be bi directional of quickly bit banged to P1 and the unused sections of P3 Then group all the remaining inputs to one 8255 port configured as in input and all the remaining outputs to another 8255 port configured as an output In most cases this will giv...

Page 10: ... point address es However the monitor isn t always successful at this You may need to re download the your code again to ensure that your code is intact Recall that the monitor uses a three byte LCALL instruction as its breakpoint trap instruction It s unfortunate that the 8051 doesn t include a single byte call instruction like the RSTn of the 8080 family This would be ideal for use by a simple m...

Page 11: ...ruction to any other location in the Program Memory space In general the first vector location 0003H jumps to EFFDH the second vector 000BH jumps to EFFAH and so on At the time this document was written the interrupt vectors were as follows Table 2 Interrupt Vectors3 ROM Adr Jumps to RAM Adr 00003H Jumps to 0EFFDH 0000BH Jumps to 0EFFAH 00013H Jumps to 0EFF7H 0001BH Jumps to 0EFF4H 00023H Jumps to...

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