Tandy 102 Service Manual Download

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Summary of Contents for 102

Page 1: ...TANDY of 0 0 CUSTOM MANUFACTURED FOR RADIO SHACK A DIVISION OFTANDY CORPORATION...

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Page 3: ...display 3 1 PART IV THEORY OF OPERATION 4 1 General 4 1 Block Diagram 4 2 CPU 4 3 Memory 4 3 I O Map 4 5 Keyboard 4 6 Cassette Interface Circuit 4 7 Printer Interface Circuit 4 8 Bar Code Reader Inte...

Page 4: ...CB Views 7 3 APPENDIX A INSTALLATION A 1 Installation of Optional RAM and ROM A 1 APPENDIX B KEYBOARD LAYOUT CONNECTOR PIN ASSIGNMENTS AND CHARACTER CODE TABLE B 1 B 1 Keyboard Layout B 1 B 2 Connecto...

Page 5: ...nterface 4 14 4 15 RS 232C MODEM Selection Circuit 4 15 4 16 RS 232C Interface Circuit 4 16 4 17 MODEM IC and Peripheral Circuit 4 17 4 18 Transmission Filter Circuit 4 17 4 19 Reception Filter Circui...

Page 6: ...Detection Timing C 18 C 16 Construction of LCD Panel C 19 C 17 Operation Theory of LCD Panel C 20 List of Tables TABLE NUMBER DESCRIPTION NUM PAGE BER 4 1 I O MAP 4 5 4 2 Port Address of PIO 4 5 4 3...

Page 7: ...rocedures Section III This section describes the maintenance of the Tandy 102 Section IV This section describes the general theory of operation for the Tandy 102 SectionV This section describes how to...

Page 8: ...Power Switch Move this switch towards the front to turn the power on To conserve the batteries the Tandy 102 automatically turns the power off ifyou do not use it for 10 minutes in default setting 4...

Page 9: ...via the Tandy 102 s built in MODEM connect the round end of the optional extra MODEM cable to this connector 6 CASSETTE Recorder Connector To save or load information on a cassette tape connect the c...

Page 10: ...ote that the RAM will not be backed up when this switch is set to the OFF position 2 Optional ROM and RAM Compartment An optional extra ROM and RAM can be inserted into this compartment to enhance the...

Page 11: ..._4 F q0 a V90 540 050 YD iF 4 F vw iF 980 8 a m q S0 9N0 oqr m Battery for I Memory Back up 9N3N rt Zx RAM 8KBx3 RAM HUM 1 N X 2119 ROM J a 09 5815 f 801 RAM 6119 8OC85 IZN 8IC55 e IM6402 ZZ19 Figure...

Page 12: ...HD44102 u q LED 80 40 65 40 65 4I c j 64 HD 4I 64 HD u 44102 a u 44102 Du u u C20 C19 41 40 64 M9 65 HD44102 25 80 41 40 24 25 64 M8 65 HD44102 80 40 65 40 41 64 HD 41N C14 44102 N u u C18 41 40 64 M...

Page 13: ...trokes 5 millionskeystrokes 240 x 64 full dot matrix 1 32 duty 1 6 66 bias 0 8 x 0 8 mm 0 73x0 73 mm 191 2 W X 50 4 D mm Four type AA Alkaline manganese batteries 5 days Typ 4 hours per day 20 days Ty...

Page 14: ...terface standards Handshake signals Audio cassette interf ace Data rate Input level Output level Bar codereaderinterf ace Input level TXR Transmit Data RXR Receive Data RTS Request to Send CTS Clear t...

Page 15: ...upper and lower cases are secured by snaps Pull up the front of the upper case first as shown below Also do not apply too much force when pulling it A Figure 2 1 Top Case Removal Keyboard and LCD PCBs...

Page 16: ...Main PCB 1 Remove the insulator board 2 Remove 2 screws B securing the main PCB and bottom case 3 Remove the main PCB B U 0 C CD U Figure 2 3 Main PCB Removal...

Page 17: ...y 1 To avoid operational trouble always keep the Tandy 102 clean 2 Clean the body and the LCD screen using a soft dry lint free cloth 3 For tough stains clean the body or the LCD screen with benzol Ca...

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Page 19: ...e Printer Interface Circuit Serial Interf ace Circuit Bar Code Reader Interface Circuit LCD fRS 232C LCD Common MODEM Driver Selection Circuit RS 232C LCD Segment Interface Circuit Driver MODEM IC LCD...

Page 20: ...terface RS 232C or MODEM The input output for a cassette recorder and the input of the BCR are controlled by CPU directly through its SOD SID and RST5 5 terminals ROM and RAMs are connected to the sys...

Page 21: ...of a 32 KBstandard ROM three 8 KBC MOS static RAMs and a 32 KBoptional ROM The standard RAMs equipped in the Tandy 102 are M9 M8 and M7 By installing M6 memory capacity can be increased to 32 KB The...

Page 22: ...s shown in the memory map the address space is positioned from OOOOH to 7FFFH The chip select signals are generated by the A15 and STROM signals The ADO is latched at M14 by the WR signal and Y6 signa...

Page 23: ...s circuits made by user 80 8FH YO L Device select signal for optional I O controller unit Enable signal for relay RY3 in MODEM connector 90H 9FH Y2 L interface circuit BOH BFH Y3 L PIO 81C55 chip sele...

Page 24: ...The condition of pressing the T key is shown in the figure below 33KX8 KR7 17 AD7 L AD IS KR6 16 M AD 5 KR5 15 N AD4 M15 KR4 14 B M3 AD3 KR3 43 V A02 KR2 12 C AD 1 KR1 11 x KRO 110 ADO Z 82PXB K KEYB...

Page 25: ...or circuit consisting of M30 Finally the signal is converted into the digital signal and sent to the SID terminal of the CPU In this circuit D7 clamps the negative voltage output of the comparator Rem...

Page 26: ...s the one character corresponding with the 8 bit parallel data After completion of the one character printing the printer sets the BUSY signal to L Then the CPU sends the next 8 bit parallel data Ifth...

Page 27: ...e CPU of an interruption As soon as RST5 5 interruption occurs the CPU starts the data input operation passing through the PC3 of the PIO As the bar code reader is moved across the bars H and L signal...

Page 28: ...C PIO Timer Output In this method the buzzer is sounded by setting the PIO timer in the square wave output mode To write the value corresponding to the sound frequency the CPU assigns B4H B5H BCH or B...

Page 29: ...D6 Address and data signal bit 6 12 AD7 Address and data signal bit 7 13 A8 Address signal bit 8 14 A9 Address signal bit 9 15 A10 Address signal bit 10 16 All Address signal bit 11 17 A12 Address sig...

Page 30: ...waves are output from the TP 4 ms cycle and one key scan occurs every 4 ms because of the RST7 5 interruption to the CPU TimeSet Sequence The CPU set 4uPD1990ACto the register shift mode with the 100...

Page 31: ...ATA OUT terminal At the same time the CPU sends the PA3 signal passing through the PIO for the read timing clock Y6 WR M26 32 768 kHz M2 RESET RESET Y y M O M U MCL F C19 0 047 J 25V VB 14 OE D DATA T...

Page 32: ...ansmission reception baud rate To transmit and receive the serial data from external devices the RS232C signal selects either MODEM or RS 232C interface During the MODEM operation the MODE signal swit...

Page 33: ...e the CL AS signal is used as the sensing signal for the ORG ANS switch and CP TL signal is used as the sensing signal for the ACP DIR switch In order to detect the carrier signal from the telephone l...

Page 34: ...haping and inverted by M24 and then converted to 5V or ground level signals by the diodes 0 GND 1 Z 2 0 TXR RTSR DTRR DSRR CTSR RXR GND 4 20 6 4584 i2 _ 13 1 VDD 35 1 R75100K R73 33K 2 1 R9 330n 110 3...

Page 35: ...ROM RECEPTION FILTERCIRCUIT SLFTEST Vss RXCAR B 12 C M13 TT C 02 7H IOOP 10 WR VDO ENABLE 0 D AD 10 MODE 7 ORIG ANS RXM 1 RS 232C MODEM J R12 TXM SELECTION CIRCUIT 1K RESET 5 RESET MB MC14412 Figure 4...

Page 36: ...and answer mode is accomplished by switching T2 T3 and T5 ON or OFF according to the ORG ANS switch position thus changing the input resistance of the filters 1st stage 2nd stage 3rd stage Intermediat...

Page 37: ...4 3 Connect an AC voltmeter across the above dummy load 4 Set up the Tandy 102 in BASIC mode and enter the following command to generates the carrier signal OUT 178 47 ENTER OUT 168 02 ENTER 5 Adjust...

Page 38: ...elay RY3 separates the telephone receiver audio signal TL to prevent interference RY2 another relay separates the MODEM circuit and the telephone at the conclusion of use in the MODEM mode and is also...

Page 39: ...connected to the C and R terminals of M11 a timing signal is generated which controls M12 M11 can be considered to be the master IC and M12 the slave The FRM signal defines the periodic frequency of...

Page 40: ...egments each upper and lower the segment driver outputs Y41 Y50 are not used The power supplied to these ICs in addition to VDD 5V and VEE 5V also includes V1 V6 VDD and VEE are the power supplies whi...

Page 41: ...l electrode The maximum voltage applied to common electrode and segment electrode is the potential difference between V1 and V2 In addition a is the bias coefficient which determines from the standpoi...

Page 42: ...ow that the converter cannot operate There are about 20 minutes between the time when the LED lamp illuminates and the system is switched OFF Battery voltage is detected by splitting the resistance of...

Page 43: ...111 R101 DII II II 1 8K IS2076 C70 O Ip SW3 5 _ I n 1 R144 o al p u A 0 56K O x m 01 p r l 0 v 15K x A Ay In T R106 R123 1 C1 N m v C90 0 N ro n v 1 i R n m p N C 1 A N 5 ro I 33K A 3 4 A C87 O Ip N w...

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Page 45: ...he necessary information such as corresponding ICs and transistors for malfunction repair After you complete the malfunction repair re check each functional item according to the CHECK LIST You can ma...

Page 46: ...function NO 8 YES Cassette interface doesn t function NO 9 YES B C R interface doesn t function NO 10 YES RS 232C interface doesn t function NO 11 YES MODEM interface doesn t function NO 12 YES All f...

Page 47: ...cts and adapter jack Check all output voltages a VDD 5V if not check D13 C84 and ZD1 b VEE 5V if not check D15 C85 and ZD2 c VB 5V if not check T27 and T28 Is T21 oscillating If not check T22 T13 C81...

Page 48: ...ETsignal Refer to 6 Reset doesn t function Check the LCD waveform If abnormal check the LCD power supply operation amplifier Check the interface circuitry Check all ICs connected to the bus line M17 a...

Page 49: ...rvals Check the diodes on keyboard Check the return signal Check M15 M3 M26 M16 and pull up resistors R163 R170 Check the key switching no input keys END 4 Buzzer doesn t function 4 No melody is heard...

Page 50: ...32 768 kHz If not normal check X1 C17 C18 and M18 Check that a 250 Hz pulse is output from TP signal Check the clock setting ICs M14 and M25 and RESETsignal END 6 Resetdoesn t function 6 Check the RE...

Page 51: ...battery D11 and D22 Check to be sure that there is no deviation in the timing of the signal and that the level changes symmetrically when the RAM RST and RESET are switched ON OFF Check the CMOS RAM...

Page 52: ...M19 C63 and C64 Check the RXC signals Is a digital waveform input to the SID terminal of the CPU during program DATA load If not check D5 D6 M30 M34 and M19 Check the remote circuit Check the relay RY...

Page 53: ...not output check M22 M24 M35 C71 C72 and C73 Check the receive side Check ifa digital signal is input to M22 pin 20 RRI terminal during data reception Check also to be sure that the RTSR signal of pi...

Page 54: ...the M31 Rx Car terminal pin 1 If not check M22 M30 T4 T7 OT1 and RY2 Check receive side Check to be sure that the modulation signal is input to M31 pin 1 Rx Car during data reception If not check M29...

Page 55: ...hat the calendar data changes to set data 3 Keyboardtest Refer to the character code table in Appendix B and check that all keys can be input 4 Resetfunctiontest memoryprotectiontest a Warm start Pres...

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Page 57: ...VI EXPLODEDVIEW PARTS LIST Exploded View 4 1 1 2 1 V 2 0 t 6 13 11 3 1 3 11 8 c 12 Figure 6 1 Exploded View 3 1 2 3 1 1 3 1 4 16 1 1 3 6 1...

Page 58: ...472JJMP CQMB472JTH C62 Ceramic O O1 uF 50V 10 CD 103KJCP CFPD103KB C63 Mylar 0 1 F 50V 10 CC 104KJMP CQMB104KTH C64 Mylar 0 047 F 50 V 10 CC 473KJMP CQMB473KTH C65 C67 Ceramic 0 047jF 50V 80 20 CD 473...

Page 59: ...ERZ CIODK361 ADX 1864 QNHDK361AN D19 Not used D20 D22 Diode Silicon 1S2076 ADX 1763 QDSS2076 B D23 Diode Silicon HRP22 QDSHRP22XB D24 Surge Absorber ERZ C10K220 ADX 1863 QNDDK220AN D25 D26 Not used D...

Page 60: ...ND 0196EBM RJ8APJ102 R9 Not used RIO R12 Chip 1k 1 8W t5 ND 0196EBM RJ8APJ102 R13 Metal Film 806ohm 1 4W i N 0577BEE RQBXF8060X R14 Chip lOk l 8W 5 ND 281EBM RJ8APJ103 R15 Metal Film 33 2k l 4W l N 0...

Page 61: ...333 R83 Chip 22k 1 8W 5 ND 0311EBM RJ8APJ223 R84 Chip 33k l 8W 5 ND 0324EBM RJ8APJ333 R85 Chip lOk l 8W 5 ND 0281EBM RJ8APJ103 R86 Chip 33k l 8W 5 ND 0324EBM RJ8APJ333 R87 R89 Chip 6 2k 1 8W 5 ND 0260...

Page 62: ...5 ND 0324EBM RJ8APJ333 R147 R148 Not used R149 Chip 56k l 8W 5 ND 0345EBM RJ8APJ563 R150 Chip 470ohm l 8W 5 ND 0169EBM RJ8APJ471 R151 Chip 33k 1 8W 5 ND 0324EBM RJ8APJ333 R152 Chip lOk l 8W 5 ND 0281E...

Page 63: ...2SC 2712Y QUC3052XCP T21 Silicon 2SC1384 NPN S Rank 2SC 1384 QTC1384XHN T22 Silicon 2SC2712 NPN LG 2SC 2712 QUC2712XCP T23 T25 Silicon 2SC3052 NPN No Rank 2SC 2712Y QUC3052XCP T26 Not used T27 Silico...

Page 64: ...IRCUITS M1 M5 C MOS Driver HD44102CRH MX 2169 QQ044102CB M6 M10 C MOS Driver HD44102CH AMX 5797 QQ044102BB M11 M12 C MOS Driver HD44103BLD AMX 5798 QQ044103BB M13 C MOS OP Amp LA6324 AMX 5796 QQF06324...

Page 65: ...22SBO18 1 2 17 Keytop F AK 5221 VK122SBO19 1 2 18 Keytop G AK 5222 VK122SB020 1 2 19 Keytop H AK 5223 VK122SBO21 1 2 20 Keytop I AK 5224 VK122SB022 1 2 21 Keytop J AK 5225 VK122SB023 1 2 22 Keytop G A...

Page 66: ...SBOO7 1 2 54 Keytop SHIFT AK 5654 VK132SBOO8 1 2 55 Keytop ENTER AK 5655 VK142SB003 1 2 56 Keytop SPACE AK 5261 VK172SBOO2 1 3 Diode Silicon 1S2076 ADX 1763 QDSS2076 B 1 4 Switch Key Tact AS 2910 SK01...

Page 67: ...ACS 0100 ZBN036102Y 3 9 Buzzer KBS 27DB 3T ZYED10006 4 Case Assembly Top Ivory AZ 0011 AM102 01 4 1 Case Top Ivory VB883SH004 4 2 Filter VS868AC005 4 3 Plate Model VVM102 2 5 Case Assembly Bottom Bla...

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Page 70: ...as Cs I U e U 0 p m p p I nn nnn U N7 NW U 0 Ngagmh V U a00a 000000 M3 HD44102CH CL q U NO N U 9 1 Figure 7 2 LCD PCB Schematic Diagram D a a 0 U 0 0 p0 an 5 a x 240 x 64 Full Dot LCD 32 duty 6 bias L...

Page 71: ...PCBViews R156 W77 M34 4013 111 1 01667 CO rF MI __ R68 M43 4 M231 1 3 7 4011 Figure 7 3 Main PCB Top View M37 pv15 40H245 I 40 H373 40H367 M32 4584 7 3...

Page 72: ...I1MS f 8 6t6 sI6 WY sz 6 are U 4F iF ter ID 1I 693 543 093 W 42 973 Etc _ Y h _ U IIEti 6S3y 1 SVI j 500b9L 667 9 0 3 I FT E93 4V 10 F Z0 v N 9 4 330 OMS 80 N 010 r 60 4 0 Figure 7 4 Main PCB Bottom...

Page 73: ...HO N HO N HD N HO C2 44102 TO U 44102 a 0 44102 44102 U U U 18 G20 019 64 M7 64 ml0 64 M8 41 64 41 64 M9 41 c LED 65 40 65 40 65 40 65 HO 4102 HD I H 1 2 HD4 1 2 80 2425 80 25 s0 25 24 0 24 80 24 25 8...

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Page 75: ...AM and ROM Using a coin remove the RAM and ROM cover on the bottom case Insert the optional RAM into the IC socket marked M6 Insert the optional ROM into the IC socket marked M11 CP Optional RAM a 4 O...

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Page 77: ...E TABLE B 1 KeyboardLayout TANDY 102 PORTABLE COMPUTER OO LAINMrTm BREAK 00 O1OO PAUSE PASTELABELPRINT 11 ESC FI F2 F3 F4 F5 F6 F7 F8 i i A DEL a 3 6 9 7 8 BK DDooaoao o Cf 0 0 l O TAB G O O li I P I...

Page 78: ...al bit 12 18 A13 Address signal bit 13 19 A14 Address signal bit 14 20 A15 Address signal bit 15 21 GND 22 GND 23 RD Read enable signal 24 WR Write enable signal 25 10 M I O or memory select signal 26...

Page 79: ...set ready 7 GND 8 CD Carrier detect 9 NC 10 NC 11 NC 12 NC 13 NC 14 NC 15 NC 16 NC 17 NC 18 NC 19 NC 20 DTR Data terminal ready 21 NC 22 NC 23 NC 24 NC 25 NC Description Table B 2 RS 233C Connector P...

Page 80: ...25 BUSY 26 NC 0 25 26 23 24 Description STROBE Pulse Bit 0 of Print Data Bit 1 of Print Data Bit 2 of Print Data Bit 3 of Print Data Bit 4 of Print Data Bit 5 of Print Data Bit 6 of Print Data Bit 7...

Page 81: ...NC 8 NC Figure B 5 Cassette Connector B 2 5 MODEM Interface Pin No Symbol Description 1 TL Conventional Telephone Unit 2 GND 3 R x MD Direct Connection to Tel Line RING 4 R x MC Acoustic Coupler Conn...

Page 82: ...BarCode ReaderInterface Pin No Symbol 1 NC 2 RxDB 3 NC 4 NC 5 NC 6 NC 7 GND 8 NC 9 VDD Description Receive data from bar code reader 1 2 3 4 5 0 0 0 0 0 0 0 0 0 6 7 8 9 Figure B 7 Bar Code Reader Conn...

Page 83: ...00 SPACEBAR 8 08 00001000 CTRL I H 33 21 00100001 9 09 00001001 CTRL 1 34 22 00100010 10 OA 00001010 J 35 23 00100011 11 OB 00001011 CTRL K 36 24 00100100 12 OC 00001100 CTRL L 37 25 00100101 13 OD 00...

Page 84: ...010010 R R 58 3A 00111010 83 53 01010011 8 S 59 3B 00111011 p 84 54 01010100 T T 60 3C 00111100 85 55 01010101 U U 61 3D 00111101 86 56 01010110 V v 62 3E 00111110 87 57 01010111 w w 63 3F 00111111 88...

Page 85: ...133 85 10000101 It 109 6D 01101101 m m 134 86 10000110 h 110 6E 01101110 m n 135 87 10000111 t 111 6F 01101111 0 0 136 88 10001000 it 0 1 112 70 01110000 P p 137 89 10001001 r 113 71 01110001 q q 138...

Page 86: ...AC 10101100 173 AD 10101101 174 AE 10101110 t O S COIE ca1E FCM R Y p Decimal Hex Binary 175 AF 10101111 176 BO 10110000 177 131 10110001 178 B2 10110010 179 B3 10110011 180 B4 10110100 181 B5 101101...

Page 87: ...0 213 D5 11010101 214 D6 11010110 215 D7 11010111 216 D8 11011000 217 D9 11011001 218 DA 11011010 219 DB 11011011 E 6 220 DC 11011100 221 D D 11011101 222 DE 11011110 223 D F 11011111 224 ED 11100000...

Page 88: ...Decimal Hex Binary 250 FA 11111010 251 FB 11111011 252 FC 11111100 253 FD 11111101 254 FE 11111110 255 FF 11111111 Displayed Keyboard Character Character GRPR I K F EH 1oPR T 4 RRPX G sRPX Y GRPH I C...

Page 89: ...FLAG 5 FLIP FLOP B 8 C 8 REG REG ARITHMETIC LOGIC INSTRUCTION DECODER REG 8 REG E 8 UNIT H 8 L 8 REGISTER ALU MACHINE CYCLE REG REG ARRAY ENCODING STACK POINTER 16 PROGRAM COUNTER 16 INCREMENT ER DEC...

Page 90: ...e of these lines RD Output 3 state READ control A low level on RD indicates the selected memory or I O device is to be read and that the Data Bus is available for the data transfer 3 stated during Hol...

Page 91: ...errupt Disable It has the highest priority of any in terrupt See Table C 1 RESET IN Input Sets the Program Counter to zero and resets the Interrupt Enable and HLDA flip flops The data and address buse...

Page 92: ...These lower 8 bits may be latched externally by the Address Latch Enable signal ALE During the rest of the machine cycle the data bus is used for memory or I O data The 80C85A provides RD WR So Si an...

Page 93: ...ept TRAPs until an El instruction is executed The TRAP interrupt is special in that it disables interrupts but preserves the previous interrupt enable status Performing the first RIM instruction follo...

Page 94: ...W 1 0 1 1 0 1 Acknowledge of INTR INA 1 1 1 1 1 0 Bus Idle BI DAD ACK OF 0 1 0 1 1 1 RST TRAP 1 1 1 1 1 1 HALT TS 0 0 TS TS 1 Table C 2 80C85A Machine Cycle Chart Status Buses Control Machine State Si...

Page 95: ...00 ns the MSM81 C55RS GS can be used in an 80C85A system without using wait states The parallel I O consists of two 8 bit ports and one 6 bit port both general purpose The MSM81C55RS GS also contains...

Page 96: ...RD input Ifthis pin is low data from either the memory or ports is read onto the ADo 7 lines depending on the state of the IO M line WR Input If this pin is low data on lines ADo 7 is written into eit...

Page 97: ...imer Timer mand t MSB LSB Status Timer Mode 6 bits 8 bits 8 bits Figure C 7 Internal Register of 81 C55 I O Address Selecting Register A7 A6 A5 A4 A3 A2 Al AO X X X X X 0 0 0 Internal command status r...

Page 98: ...sthe timer if it is running NOP ifthe timer is not running 10 STOP AFTER TC Stopsthe timer when it reaches TC NOP ifthe timer is not running 11 START Ifthe timer is not running loadsthe mode and the c...

Page 99: ...er xxxxx010 4 PC Register The PC register may be used as an input port output port or control register depending on the pro grammed contents of the C S register The I O address of the PC register is x...

Page 100: ...ignal count operation stops but the counter is not set to a specific initial value or output mode When restarting count opera tion after reset the START command must be executed again through the C S...

Page 101: ...its code THE TBR8 MS1B TBRICLSBI TBRE I PARITY RANSMITTER BUFFER REGISTER I TBRL TRANSMITTER STOP LOGIC RANSMITTER REGISTER START I TIMING TRC CONTROL MULTIPLEXER I CLSI CONTROL CLS2 REGISTER MR I RRC...

Page 102: ...DR Output EA high level on DATA RECEIVED indicates a character has been received and transferred to the receiver buffer register RRI Input Serial data on RECEIVER REGISTER INPUT is clocked into the r...

Page 103: ...bits CLS1 low CLS2 high 7 bits CLS1 high CLS2 high 8 bits EPE Input When PI is low a high level on EVEN PARITY ENABLE generates and checks even parity A low level selects odd parity TRC Input The TRA...

Page 104: ...unused most significant bits will be a low level The output character is right justified to the least significant bit RBR1 A high level on OE indicates overruns An overrun occurs when DR has not been...

Page 105: ...B The rising edge of TBRL clears TBRE 0 to 1 clock cycles later data is transferred to the transmitter register THEis cleared TBRE is set high and serial data transmission is started Output data is c...

Page 106: ...s clock count 7 1 2 Ifthe receiver clock is a symmetrical square wave the center of the start bit will be located within 1 2 check cycle 1 32 bit or 3 125 giving a receiver margin of 46 875 The receiv...

Page 107: ...ectric shutter that controls the passage of light Ifvoltage is applied the transmission of light is blocked otherwise light is allowed to pass so that letters and numbers can be displayed Figure C 17...

Page 108: ...l Light Front Polarizer Front Glass Electrode b Voltage is applied ti ru OFF Rear Glass Electrode I Rear Polarizer Reflector Light is passed Light is interrupted Bright Dark Figure C 1 7 Operation The...

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Page 110: ...N U S A FORT WORTH TEXAS 76102 CANADA BARRIE ONTARIO L4M 4W5 TANDY CORPORATION AUSTRALIA BELGIUM UK 91KURRAJONG AVENUE PareIntlustriel BILSTON ROAD WEDNESBURY MOUNT DRUITT NSW 2770 5140Naninne Namur W...

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