Tally T9020, Maintenance Manual

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• Video data transfer
– When the mechanism controller starts the motor, paper moves along the paper path.
The mechanism controller checks the sensor on the paper path. When paper reaches
the position where video data needs to be created, the main controller starts video
data transfer from the LSI-1. The LSI, under control of DMA, starts to transfer bit
map data from bit map memory to internal buffer memory. The data stored in buffer
memory is transferred to the FEIT LSI in synchronization with the clock signal
(CLD) generated by the FEIT LSI. The controller generates other signals such as
latch and strobe pulses for the LD unit.
The timer circuit generates an original timing signal for each raster, based on which
the video timing controller generates the above three signals.
– The FEIT circuit in the LSI receives image data from the video buffer in the LSI-1. It
then calculates image data for image improvement and sends the calculation results as
video data to the LD unit in synchronization with the BD signal. The BD signal is
used to detect that the laser beam is at the start position and that video data transfer is
requested. The BD signal is generated as a synchronization signal for each raster
from the LD unit.
Figure 5220-9 is a video data transfer block diagram.
CPU RAM bit memory map
Controller
DMA
LSI
Buffer FEIT
Timer
Video
timing
Print
density
conversion
LSI
DIN
CLK
LD unit
• LD unit
The LD unit consists of the spindle motor controller and laser power controller.
GID 5220
Figure 5220-9 Video data transfer block diagram