Tadpole SPARCbook 3 series, Reference Manual

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11-20
Display Interface
Direct frame buffer access
Bits 15:13 Reserved (contains zeroes)
Bits 12:00 Minimum or Maximum y values
11.2.11 RAMDAC register accesses
Accesses to the RAMDAC’s internal registers are made through locations
within the Power 9100’s address space, see Section 11.4.1, “RAMDAC
host interface”, on page 11-22
11.3 Direct frame buffer access
To the host, the framebuffer appears as a normal 2 Mbyte linear memory
array. With 8 bit pixels, each byte in the framebuffer represents 1 pixel on
the display and the lowest addressed location in the framebuffer appears at
the top left of the display; that is the pixel at the top left of the display (pixel
0) is addressed at 0x30200000. The top left pixel on the display is fixed at
this address in memory. Panning and zooming is carried out by redrawing
the image in the framebuffer.
Pixel data is packed into the framebuffer so that adjacent lines on the
display start at line-length address intervals. For example, the first pixel on
the second line of a 640 x 480 pixel display would be addressed at
0x38800280. Figure 11-4 illustrates the framebuffer addressing for two
Figure 11-4 Frame Buffer Addressing
0x38800000
0x38800280
0x3884AD80
Lines Visible on Display
640 x 480 x 8 bit pixels
0x38800000
0x38800800
0x389C1800
1024 x 900 x 16 bit pixels
0x3884B000
0x38A00000
0x38A00000
Lines Visible on Display
Not Visible on Display
Not Visible on Display
0x389C2000
S3GX_TRMBook Page 20 Friday, September 19, 1997 11:39 am