Tadpole SPARCbook 3 series, Reference Manual

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Parallel Interface
10-3
Parallel Port Control Registers
sequence of DMA transfers of equal size from different addresses; only the
NEXT Address Register need be updated and the DMA controller will
simply load its new contents and the existing contents of the NEXT Byte
Counter.
10.2 Parallel Port Control Registers
The parallel port registers are located at the addresses shown in Table 10-1.
Control and Status
Register
This register provides DMA status and control for the parallel port. It is a
32-bit read-write register, which contains a number of read-only status bits
and read-write control bits.
Bits 31:28 Device ID (= 1010)
Bit 27 Next Address Loaded (read-only) – this bit is set when the
NEXT Address and Byte Count registers have been written
but have not been used.
Bit 26 Address Loaded (read-only) – is set when the contents of the
address and byte count are considered valid during chained
transfers.
Address Register Size Access
0x7C800000 Control and Status Register 32 R/W
0x7C800004 Address Register 32 R/W
NEXT Address Register 32 R/W
0x7C800008 Byte Count Register 32 R/W
NEXT Byte Count Register 32 R/W
0x7C80000C Test Control and Status Register 32 R/W
0x7C800010 Hardware Configuration Register 16 R/W
0x7C800012 Operation Control Register 16 R/W
0x7C800014 Parallel Data Register 8 R/W
0x7C800015 Transfer Control Register 8 R/W
0x7C800016 Output Register 8 R/W
0x7C800017 Input Register 8 R/W
0x7C800018 Interrupt Control Register 16 R/W
Table 10-1 Parallel Port Control Registers
S3GX_TRMBook Page 3 Friday, September 19, 1997 11:39 am