Tadpole SPARCbook 3 series, Reference Manual

Page: 122 / 216

9-4
MODEM
Modem Registers
9.3 Modem Registers
This section describes the more significant registers from the point of view
of managing the flow of commands and data between main memory and the
modem.
9.3.1 Interrupt Enable Register
This register contains interrupt control bits. Setting one of the interrupt
enable bits has the effect of enabling the associated interrupt request.
Bits 7:4 Reserved
Bit 3 Enable Modem Status Interrupt
Bit 2 Enable Receiver Line Status Interrupt
Bit 1 Enable Transmitter Holding Register Empty Interrupt
Bit 0 Enable Received Data Available Interrupt
9.3.2 Interrupt Identification Register
This register provides the identity of the highest priority pending interrupt
condition, and a flag which indicates whether or not there is an interrupt
pending. The MCU prioritizes the internal interrupt requests as shown
below.
Bit 7:3 Reserved
Bit 2:1 Interrupt ID
11 = Receiver Line Status – highest priority
10 = Receiver Data Available
01 = Transmit Buffer Empty
00 = Modem Status – lowest priority
Bit 0 Interrupt Pending Flag
1 = No Interrupt Pending
0 = Interrupt Pending
S3GX_TRMBook Page 4 Friday, September 19, 1997 11:39 am