Tadpole SPARCbook 3 series, Reference Manual

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ISDN and 16-bit Audio
8-17
Audio CODEC
11. Set the D/C line high to place the codec in data mode. The codec will
execute an offset calibration cycle
12. Transmit or receive audio data.
8.3.2 Control Mode
Conrol information can be written to the audio codec, and status can be read
while is is in the control mode. The audio codec is placed in control mode
via the DBRI bit port PIO3. There are six 8-bit internal registers which are
each assigned to a time slot. The slots to which the registers are assigned
are shown in Table 8-4.
The registers of most interest are described briefly below.
Status Register
Bit 3 OLB – Output Level Bit.
0 = Full scale outputs are:
Line 2.8 Vpp; Headphone 4.0 Vpp; Speaker 8.0 Vpp.
1 = Full scale for Line and headphone are 2.0 Vpp;
Speaker 4.0 Vpp
Bit 2 CLB – Control Latch Bit. This bit is used to ensure proper
transition between control and data modes
Time Slot Register
1 Status
2 Data Format
3 Serial Port Control
4 Test
5 Parallel Port – Not used
6 Reserved
7 Revision
8 Reserved
Table 8-4 Audio Codec Control Registers
OLB
CLB
7
3
2
4
1 0
5 6
S3GX_TRMBook Page 17 Friday, September 19, 1997 11:39 am