SYS TEC electronic GmbH
L-1589e-04
Hardware Manual ECUcore-1021
Page 23/30
Classification: Release
3
Design-in Considerations
3.1
Power Supply Design considerations
This section provides design recommendations for the power supply of ECUcore-1021. For information
about module power supply values and power consumption see Table 2.
The ECUcore-1021 is powered by a single power rail (see Table 2). The power supply inputs are 3V3 and
3V3_D1VDD. The 3V3_D1VDD-input is an always-on rails instead the 3V3 input, which can be switched-
off during Deep Sleep Mode (DSM). Some of the on-board components are supplied from input rails
directly. So the power supply rail must be met closely the requirements of product specification.
The signal levels of the module interface depend on the configured interface type. The carrier board
designer must note this fact if he connects the peripherals to the module. Otherwise, it may be
overloaded or destructed. See sec. 2.4 for more information of signal levels.
The module supply should be slew rate limited to no more as 2.5mV/ms.
The on-board processor needs different power rails to support the configurable interfaces. Following
power rail configuration is used:
Power rails
Value
Applied interfaces
BVDD
3.3V
QSPI, SPI1, IFC, FTM5, FTM6, FTM7, I2C, GPIO3
EVDD
3.3V
GPIO2, eSDHC, LPUART3, 5, 6
D1VDD,
DVDD
3.3V
DUART, I2C, DMA, QE, TDM, 2D-ACE, LPUART1, 2, 4, GPIO1, eSDHC,
SAI(I2S) 3, 4, SPDIF, FTM4, FTM8, SPI2, IRQ
LVDD,
L1VDD
2.5V
EC1, EC2, EC3, EMI1, GPIO1, GPIO3, CAN1-4, FTM1-3, SAI (I2S)1-2
Table 8: Overview of configured on-board power rails
3.2
Power-on RESET and RESET Configurations
After power supply is applied to the module and all internal power rails reach the required output value
the signal /PORST is de-asserted after 140ms
– 280ms. After the rising edge of /PORST the reset control
logic of LS1021A begins cycling the device through its full reset and RCW configuration process. Note the
recommendation in Table 5 and Table 6 to read the right RCW value from the input pins.
3.3
Manual RESET (/MR)
A reset occurs if the manual reset (/MR) is switched to GND. The signal input must be driven by an open-
drain output or can be connected with an RESET button. The signal input has an internal pull-up resistor.
3.4
System Booting
The Module supports the on-board QSPI NOR-Flash memory or a device connected to the eSDHC
interface of module. The boot device is selected by the pre-boot loader of LS1021A via pin IFC_AD14. If
IFC_AD14 is set to low during a power cycle, the pre-boot loader selects the eSDHC as boot device
interface instead of on-board QSPI NOR-Flash. The pre-boot loader of LS1021A performs configuration
register reads and writes to initialize the boot device interface, loads the RCW and pre-boot initialization
commands form the boot device, and writes data to configuration registers before the local cores of
LS1021A are permitted to boot.
3.5
General interface design consideration
For design-in of standard interfaces like PCIe2.0, Ethernet, SGMII, SATA3.0 or USB3.0 the rules of high
speed design should be noted. Important parameters are the signal line impedance, the signal line length,
