Precharge to Active (3T/4T)
This item is used to designate the minimum Row Precharge time of the
SDRAM devices on the module.
DRAM must continually be refreshed or it will lose its data. Normally, DRAM is
refreshed entirely as the result of a single request. This option allows you to
determine the number of CPU clocks allocated for the Row Address Strobe (RAS)
to accumulate its charge before the DRAM is refreshed. If insufficient time is
allowed, refresh may be incomplete and data lost.
Active to Precharge (6T/10T)
This item specifies the number of clock cycles needed after a bank active
command before a precharge can occur.
Active to CMD (3T)
This item specifies the minimum required delay between activation of different
rows.
DRAM Burst Length (4)
This item describes which burst lengths are supported by the devices on the
mainboard. 1 level can provide faster performance but may result in instability
whereas 8 level gives the most stable but slowest performance.
DRAM Queue Depth (4 level)
This item sets the depth of the DRAM queue used for CPU’s cache.
DRAM Command Rate (2T Command)
This item enables you to specify the waiting time for the CPU to issue the next
command after issuing the command to the DDR memory. We recommend
that you leave this item at the default value.
Press <Esc> to return to the Advanced Chipset Setup screen.
AGP & P2P Bridge Control
Scroll to this item and press <Enter> to view the following screen:
CMOS Setup Utility – Copyright (C) 1984 – 2001 Award Software
AGP & P2P Bridge Control
Item Help
AGP Aperture Size
[128M]
AGP
Mode
[4X]
AGP Driving Control
[Auto]
x AGP Driving Value
DA
Menu Level
↑
↓
→
←
: Move Enter : Select
+/-/PU/PD:Value:
F10: Save ESC: Exit F1:General Help
F5:Previous
Values
F6:Fail-Safe
Defaults F7:Optimized
Defaults
33
