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SCR1 SDK. Digilent Arty Edition.

Quick Start Guide

Syntacore, [email protected]

Version 0.2, 2018-09-25

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Summary of Contents for SCR1 SDK

Page 1: ...SCR1 SDK Digilent Arty Edition Quick Start Guide Syntacore info syntacore com Version 0 2 2018 09 25...

Page 2: ...1 5 4 Onchip Memory Update 11 5 5 Configuration FLASH Updating 12 6 Appendix A JTAG Pin Out 13 7 Appendix B SDK Memory Map 14 8 Appendix C SDK IRQs 15 9 Appendix D SDK Memory Mapped Registers 16 9 1 P...

Page 3: ...contained in this material is confidential and proprietary to Syntacore LLC and its affiliates and may not be modified copied published disclosed distributed displayed or exhibited in either electroni...

Page 4: ...Revision history Version Date Description 0 1 2017 09 09 Initial revision 0 2 2017 09 25 Updated for Vivado 2018 1 compatibility 2...

Page 5: ...er guide allowing to get started with SCR1 SDK based on Arty FPGA Development Board from Digilent It describes the board setup procedure of software uploading and launching and process of the FPGA s c...

Page 6: ...OpenOCD you need also JTAG Cable Adapter Olimex ARM USB OCD H or ARM USB OCD https www olimex com Products ARM JTAG ARM USB OCD H Standard USB Type A m Type B m cable Wire Connection between JTAG Cabl...

Page 7: ...J10 Shared USB JTAG UART port and your host computer This connection performs three functions 5V Power Supply for Arty FPGA Configuration JTAG port Serial Port for console interface with running softw...

Page 8: ...E Please take into account that Olimex USB JTAG cable adapters after powering up just after their USB cable connecting hold debug connector s SRSTn line in asserted state actively holding entire proce...

Page 9: ...r1_top_new mcs arty_scr1_top_new prm 3 3 Procedure 1 Launch Vivado tool 2 Open Hardware Manager then open appropriate target 3 In the FPGA device s context menu right click select Add Configuration Me...

Page 10: ...loader s banner and prompt SCR loader v1 0 scr1_RC Copyright C 2015 2017 Syntacore All rights reserved ISA RV32IMC 40001104 IMPID 17090700 SYSID 17090400 BLDID 17090701 Platform arty_scr1 cpuclk 25MHz...

Page 11: ...M upload menu In minicom terminal you need to press Ctrl A and press S Then select xmodem Upload zmodem ymodem xmodem kermit ascii 5 In this example we use binary file with Dhrystone benchmark which c...

Page 12: ...o3lto bin to the TCM base address 0xf0000000 as described in the previous section 2 Select g menu item then enter the test s launching address 0xf0000200 That will start program execution 1 xmodem loa...

Page 13: ...scr1 tcl creates Vivado project arty_scr1 and prepares used IPs for further synthesis 5 3 Building Bitstream File In the just deployed and open project click on Project Navigator Program and Debug Gen...

Page 14: ...arty runs impl_1 should contain updated bit file arty_scr1_top_new bit and MCS file arty_scr1_top_new mcs for configuration FLASH chip programming 5 5 Configuration FLASH Updating Refer to the section...

Page 15: ...ix A JTAG Pin Out SCR1 JTAG port is routed to the onboard Pmod connector JD in accordance with Table 1 Table 1 SCR1 JTAG Pin Out Net JD bit PMod JD pin TRSTn 2 3 TCK 3 4 TDO 4 7 TDI 5 8 SRSTn 6 9 TMS...

Page 16: ...core 0xFF000000 4 kB SYS_ID 32 bit System ID register 0xFF001000 4 kB BLD_ID 32 bit Build ID register 0xFF010000 4 kB UART 16550 UART registers refer to Xilinx IP description for details Interrupt lin...

Page 17: ...8 Appendix C SDK IRQs Table 3 SCR1 IRQ Mapping IRQ line Device Notes 0 UART Xilinx 16550 UART IP 1 BTN Xilinx PIO input register connected to 4 onboard push buttons 15...

Page 18: ...onboard LD2 9 11 LED3 LED 3 control onboard LD3 9 2 PIO_LED Programmable IO LED Control Register 0xFF020008 Table 5 Programmable IO LED Control Register Bit s Name Description 0 LED0 LED 0 control co...

Page 19: ...l mem for Digilent Arty 10 2 Zephyr OS 10 2 1 Getting the sources git clone git github com syntacore zephyr git 10 2 2 Building Zephyr OS Follow the instructions in https www zephyrproject org doc get...

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