DWC ADC 12b5M SAR, TSMC180 IP Databook
April 2012
Synopsys, Inc.
8-30
5
Pin Description
Pin Name
I/O Type
Function
vinp18 .. 0
I
Analog
Analog input signals
In differential input mode (
seldiff
=H),
vinp
18...
vinp
1 are the positive inputs,
vinn
18...
vinn
1 are
the negative inputs.
vinp0
available only for single ended input mode.
vinn18 .. 0
I
Analog
Analog input signals
In single ended input mode (
seldiff
=L), the negative input
vinn
0 must be connected to
ground.
vrefp
I
Analog
Positive Reference Voltage,
The reference voltage must be applied externally to the
vrefp
pin, in order to define the ADC
full scale input range.
This pin presents a sw itched capacitive load to its driver, that w ill be around 3pF in w orst
case. The sw itching frequency is the clock frequency. The
vrefp
input impedance w ill vary
through the conversion cycle, betw een the described 3pF and a negligible capacitor value of
around 1fF.
agndref
I
Analog
Negative Reference Voltage
The reference ground voltage must be applied externally to the
agndref
pin, in order to define
the ADC full scale input range
atstbus
I/O
Analog
Internal voltage regulator analog probing test signal.
Under ADC test mode it is mandatory to have direct access to this signal from chip pinout
or
through registers.
selres1 .. 0
I
Digital
Selects the ADC resolution:
selres
=00
6-bit mode
selres
=01
8-bit mode
selres
=10
10-bit mode
selres
=11
12-bit mode
seldiff
I
Digital
Selects the ADC input mode (18 selectable inputs are available in both configurations,
vinp0
|
n0
is available only for single-ended mode):
seldiff
=L
single ended inputs
seldiff
=H
differential input
dislvl
I
Digital
(3.3V)
This digital input signal must have 3.3 V levels (avdd).
This signal is used for tw o purposes:
1.
When there is no digital supply (
dvdd
) but the analog supply (
avdd
) it is pow ered on,
activating this signal (
dislvl
= H) prevents current consumption on analog supply (
avdd
)
during digital supply (
dvdd
) startup.
2.
This signal is also used to control the pow er sw itching of
dvdd
inside the IP, defining the
deep pow er dow n mode.
sel4..0
I
Digital
Input multiplexer control signals:
- vinp|n0 selected when sel4..0=0H
- vinp|n
18 selected w hen
sel
4..0=12H;
Under ADC test mode it is mandatory to have access to this signal, directly from chip pinout
or
through registers.
resetadc
I
Digital
Reset of internal buffers and registers (Active H).
Under ADC test mode it is mandatory to have direct access to this signal from chip pinout
or
through registers.
soc
I
Digital
Start-of-conversion signal (Active H). Starts the conversion cycle on the next clk rising edge.
Under ADC test mode it is mandatory to have direct access to this signal from chip pinout
or
through registers.
clk
I
Digital
Clock Input.
Under ADC test mode it is mandatory to have direct access to this signal from chip pinout
or
through registers.
enadc
I
Digital
Enable ADC (
enadc
=H
normal operation).
enldo
I
Digital
Enable internal voltage regulator (
enldo
=H
normal operation).
enctr2.. 0
I
Digital /
Test
Digital signals to enable internal analog programmability modes used for test purposes. In
normal operation these signals should be connected in to gnd.
Under ADC test mode it is mandatory to have access to this signal, directly from chip pinout
or
through registers.
