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DWC ADC 12b5M SAR, TSMC180 IP Databook

April 2012

Synopsys, Inc.

1-30

DWC ADC 12b5M SAR, TSMC180

Databook

3640tg -12-bit, 5MSPS SAR ADC with differential 19:1 Input Mux

Version 1.9

April 2012

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Summary of Contents for TSMC180

Page 1: ...DWC ADC 12b5M SAR TSMC180 IP Databook April 2012 Synopsys Inc 1 30 DWC ADC 12b5M SAR TSMC180 Databook 3640tg 12 bit 5MSPS SAR ADC with differential 19 1 Input Mux Version 1 9 April 2012...

Page 2: ...t Analysis Columbia Columbia CE Comet 3D Cosmos CosmosEnterprise CosmosLE CosmosScope CosmosSE Cyclelink DC Expert DC Professional DC Ultra Design Advisor Design Analyzer Design Vision DesignerHDL Des...

Page 3: ...Standby Mode 12 Normal Operation 12 Current Consumption during Normal Operation 12 Internal Voltage Regulator 13 7 Timing Diagrams 14 8 Digital Offset Calibration 19 10 Application Notes 23 Cell Place...

Page 4: ...ce voltage which defines the full scale input range This reference voltage can be the analog power supply for rail to rail operation An internal voltage regulator is included in order to improve perfo...

Page 5: ...included 5 pF Analog Biasing Positive reference voltage vrefp avdd 2V 2 avdd avdd V avdd 2V avdd avdd avdd V Negative reference voltage agndref 0 0 0 1 V Digital Output Logic Family CMOS Output Logic...

Page 6: ...Consumption Fs 1MSPS 1 3 avdd dvdd enadc H soc H seldiff H 240 20 A Current Consumption Fs 10kSPS 1 3 avdd dvdd enadc H soc H seldiff H 17 1 A Current Consumption Fs 5MSPS 1 3 avdd dvdd enadc H soc H...

Page 7: ...ode seldiff L single ended mode vrefp av dd agndref 0 enldo H Parameter Conditions MIN TYP MAX Unit DNL 1 0 LSB INL 2 0 LSB SINAD4 68 dBFS Offset error Calibration enabled Calibration disabled 2 64 LS...

Page 8: ...only for single ended mode seldiff L single ended inputs seldiff H differential input dislvl I Digital 3 3V This digital input signal must have 3 3 V levels avdd This signal is used for two purposes 1...

Page 9: ...de bvos6 0 is set to 1000000 loadcal I Digital Signal that loads the offset calibration word into the internal registers Active H startcal I Digital Signal that starts the offset calibration cycle Act...

Page 10: ...ration X X X 0 1 1 0 X 0 0 1 0 The following start up sequence should be followed during system startup 1 During the power up time of the supply voltages ensure that enldo L enadc L and soc L 2 Power...

Page 11: ...rd available through bvos6 0 bus before entering deep power down mode The startup sequence from deep power down should be as follows 0 Set dislvl L 1 Set enldo H and wait for the internal voltage regu...

Page 12: ...d to receiver either single ended or differential input signals in the following way 1 By setting seldiff H vinp18 vinn18 vinp2 vinn2 vinp1 vinn1 are the positive negative pairs of differential input...

Page 13: ...which means that soc signal will only be set to high from time to time The effective current consumption reduction will depend on the time period left between each conversion cycle Please check the cu...

Page 14: ...ol signals sel0 4 must be stable during both the clock cycle immediately before and the one immediately after that edge The resolution selection control signal selres can only be updated after the end...

Page 15: ...in unchanged during this period The timing Diagram below shows the start up sequence from deep power down mode It assumes that calibration has been performed in a previous normal operation cycle and t...

Page 16: ...s immediately after conversion cycle n ends In this case the duration of the sampling phase is approximately 1 5 fclk CS must be charged in that phase and it must be ensured that the voltage at its te...

Page 17: ...period should be delayed during the necessary clock cycles to guarantee the sampling precision Figure 7 Figure 7 N Resolution that is selectable with selres The following graphics indicates the numbe...

Page 18: ...resented in this graphic were measured under worst case conditions slow process corner avdd 1 8V dvdd 1 62V Tjunction 40 C fclk 70MHz vrefp avdd 0 1 10 100 1000 0 1 1 0 10 0 100 0 Additional n of cloc...

Page 19: ...ial seldiff H respectively Part of the input capacitor array is controlled by the successive approximation circuitry which is the same used to obtain the output code in normal operation to measure and...

Page 20: ...eeds to store different calibration values e g for single ended and differential input mode By ensuring the timing constrains between loadcal and soc in the figure below bvos 6 0 are updated in the fi...

Page 21: ...Name Value during Normal Mode Value during test mode scanmode 0 1 scanen 0 Connect to PAD scanclk 0 Connect to PAD scanin 0 Connect to PAD scanout 0 Connect to PAD For scan testing the scanmode signal...

Page 22: ...chain coverage is 96 All flip flops are clocked on the rising edge of the scanclk The input data scanin pin should change synchronously with the rising edge of the scanclk clock The output data scano...

Page 23: ...nd the digital circuits produces better results with high resistive substrates The maximum noise isolation is accomplished utilizing the Deep Nwell option Any modification on the metal layers within t...

Page 24: ...specially the single ended ones using the analog ground agnd Take special attention to the routing of the input lines Any noise coupling is treated as input signal thus reducing the dynamic range of t...

Page 25: ...P must respect the range in databook s specification table agnd 1 1 n a dvdd 10 1 For full performance the supply voltage at the boundary of the IP must respect the range in databook s specification t...

Page 26: ...ties will now be illustrated The following figure shows the configuration for differential inputs with external reference voltage that is independent from supply levels vrefp and agndref is connected...

Page 27: ...ply should be made as close as possible to the pad in order to minimize the IR drop Figure 15 IO ring case 2 Separate Analog IO ring when only vrefp applied externally vrefp is connected to a pad agnd...

Page 28: ...pad respectively and the inputs are differential It is possible to mix single ended and differential inputs The ADC core contains a number of analog and digital signals that are not used in normal ope...

Page 29: ...should be done according to the figure below At least the 10nF capacitors should be ceramic good quality and must be placed as close as possible to the chip Figure 17 Power supply and reference decou...

Page 30: ...10 854 20 1690 20 1690 50 4190 50 4200 100 8350 100 8350 10 bit 0 9 10 bit 0 14 0 05 13 0 05 17 0 1 16 0 1 21 0 2 23 0 2 27 0 5 43 0 5 48 1 78 1 83 5 358 5 362 10 706 10 710 20 1400 20 1410 50 3490 50...

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