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DesignWare ARC AXC003 CPU Card User Guide
AXC003 Processor FPGA Overview
Synopsys, Inc.
Version 6323-018
May 2017
10
– Reserved
11
– Reserved
ARC HS34 Emulation
The HS36 configurations on the AXC003 CPU card also have closely coupled memories:
256k ICCM and 256k DCCM. This configuration can be used for an emulation of HS34 cores
and for working with software packages built and compiled for HS34.
The difference between HS34 and HS36 with CCM memories on AXC003 is in memory
mapping. The memory mapping of HS36 with CCM is shown in Table 18.
In HS34 emulation mode the DDR3 memory is also available, but its latency is larger than in
closely coupled memory. This mode also has data cache and instruction cache disabled.
The ARC HS36 core has internal ICCM and DCCM memories. The locations of these
memories depend on register settings in the ARC HS36 core. The pre-boot loader keeps the
ICCM at its reset address 0x1000_0000 but moves the DCCM base address to 0xC000_0000.
Therefore the ARC HS36 core can only access the RAM on the ARC SDP Mainboard using
0x0000_0000 as the base address.
The start address of DDR3 SDRAM is 0x8000_0000.
See Chapter 7
for a detailed mapping description.
Table 18
Memory mapping for ARC HS36
0xFFFF_FFFF
0xF000_0000
AXI2APB on AXC003 CPU Card (CREG)
0xEFFF_FFFF
0xE000_0000
AXI2APB on Mainboard
0xDFFF_FFFF
0xD000_0000
AXI Tunnel Slave for HAPS System
0xCFFF_FFFF
0xC000_0000
DCCM 256k
0xBFFF_FFFF
0x8000_0000
DDR3 SDRAM
0x7FFF_FFFF
0x4000_0000
Unused
0x3FFF_FFFF
0x3000_0000
Internal ROM
0x2FFF_FFFF
0x2000_0000
SRAM on Mainboard
0x1FFF_FFFF
0x1000_0000
ICCM 256k
0x0FFF_FFFF
0x0000_0000
SRAM on AXC003 CPU Card