Synopsys DesignWare ARC AXC003, User Manual, Page: 38 / 145

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DesignWare ARC AXC003 CPU Card User Guide AXC003 Processor FPGA Overview
Synopsys, Inc. Version 6323-018
May 2017
I/O Coherency
AXC003 I/O Coherency Architecture
512kB L2 cache
ICACHE DCACHE
HS38
SCU
BIU
HS38
IOC
bridge
CBU
64bit
AXI master
0BU
64bit
AXI master
IOC
64bit
AXI slave
coherent
DMA traffic
bypass port for
non-coherent
DMA traffic
IO coherency port
filtering of coherent
and non-coherent DMA
traffic based its on
address
ICCM DCCM
MMU
ICACHE DCACHE
ICCM DCCM
MMU
The AXC003 Processor FPGA supports the HS38x2 hardware I/O mechanism for ARC.
The I/O coherency architecture is illustrated Figure 24. The ARC HS38x2 provides an
additional AXI slave port (the I/O coherency port) that can be used by any DMA client that
needs to operate on cacheable data that is shared with the ARC core. Traffic on the I/O
coherency port is filtered by the IOC bridge based on its address. When it falls within a certain
(programmable) address window, the traffic is forwarded to the SCU. When it fails outside the
address window, the traffic is forwarded to it final destination without being snooped.
6.7.3.1 I/O Coherency and Physical Address Extension
The DMA clients on the AXS mainboard do not support PAE. Their physical address range is
limited to 32 bits 4 G). The limitation of 4 G physical address range causes a problem when
a DMA client needs to operate on cacheable data in the PAE region that is shared with the
ARC core. Instead, a special PAE control register is provided (see Table 16). This register
makes it possible to map coherent DMA traffic to the PAE region.
The basic principle of the PAE register is illustrated in Figure 25 on page 39. Note that the
coherent DMA client in Figure 25 uses the same physical-address map as the ARC HS38x2;
the MSB bits of the physical address are simply ignored by the DMA client.