Chapter 2: Installation
2-23
S-SA
TA
0
S-SA
TA
1
S-SA
TA
2
S-SA
TA
3
I-S
AT
A0
FAN/PCH
SP1
JSD1
JPI2C1
JPW4
JITP2
BIOS
LED3
FA
N8/CPU
2
FA
N7/CPU
1
FA
N6
FA
N5
FA
N1
FA
NA
FA
N4
FA
N3
FA
NB
JVRM_I2C
2
JVRM_I2C
1
JPG1
JPL1
JPB1
JWD1
JPW1
J4
JPW3
JPW2
3-SPGPIO3
3-SPGPIO1
3-SPGPIO2
JIPMI1
JF
1
JI2C
1JI2C
2
JL
1
JOH1
JD1
JSTBY1
JTPM
1
JBAT1
(IN X8
)
KB/MOUSE
USB2/3
IPMI_LAN
TPM/POR
T80
CPU2 Slot 7 PCI-E 3.0 x
8
CPU2 Slot 5 PCI-E 3.0 x
8
CPU1 Slot 3 PCI-E 3.0 x
8
CPU1 Slot 1 PCI-E 3.0 x
8
USB8/9 USB6/7
P2-DIMMG
1
P2-DIMMH
2
P2-DIMMH
1
P2-DIMMG
2
P2-DIMME
2
P2-DIMME
1
P2-DIMMF
2
P2-DIMMF
1
P1-DIMMD
1
P1-DIMMC
2
P1-DIMMC
1
P1-DIMMD
2
P1-DIMMA
1
P1-DIMMA
2
P1-DIMMB
1
CPU1 Slot 2 PCI-E 3.0 x
8
CPU1 Slot 4 PCI-E 3.0 x
8
CPU2 Slot 6 PCI-E 3.0 x
8
CPU1 Slot 8 PCI-E 3.0 x
8
CPU2 Slot 9 PCI-E 3.0 x
8
CPU2 Slot 10 PCI-E 3.0 x
8
CPU2 Slot
11
PCI-E 2.0 x
4
P1-DIMMB
2
COM2
UID
VGA
LAN2
LAN1
COM1
I-SA
TA
2
I-SA
TA
4
I-S
AT
A1
I-SA
TA
3
I-SA
TA
5
JPT1
USB4
USB5
JITP1
LED1
BMC CTRL
LAN
CTRL
FA
N2
LED2
JBT1
X9DRX+-F
Rev. 1.02
PCH
USB0/1
CPLD
BMC Firmware
Clock Chip
JPME
1
JPME
2
CPU1
CPU2
Front Control Panel
JF1 contains header pins for various buttons and indicators that are normally lo-
cated on a control panel at the front of the chassis. These connectors are designed
specifically for use with Supermicro's server chassis. See the figure below for the
descriptions of the various control panel buttons and LED indicators. Refer to the
following section for descriptions and pin definitions.
JF1 Header Pins
Power Button
Blue+ (OH/Fan Fail/
PWR FaiL/UID LED)
1
NIC1 Link LED
Reset Button
2
Power Fail LED
HDD LED
FP PWRLED
Reset
PWR
3.3 V
ID_UID_SW/3/3V Stby
Red+ (Blue LED Cathode)
Ground
Ground
19
20
3.3V
X
Ground
NMI
X
NIC2 Link LED
NIC2 Activity LED
NIC1 Activity LED
