2-22
X8DTG-DF User's Manual
JPW2
JPW3
J11
+
LE4
SW1
JPW1
FA
N
4
FA
N
8
FAN7
FAN3
FA
N
1
4
1
FAN2
FA
N
6
FA
N
5
JLPC80
JPCIE3
JWD1
JPL1
JPG1
LE1
LE2
JBAT1
JL1
JNMI1
JSPK1
J_UID_OW
PHY
x4 in x16 Slot
SBX 2B
SBX 1B
PCI-E 2.0
SBX 2A
IPMB
T-SGPIO0
IPMI_LAN
USB2/3
SBX 1A
P2 DIMM1A
P1DIMM3A
P2 DIMM1B
P1 DIMM2B
P2 DIMM2A
P1 DIMM2A
P2 DIMM2B
P1 DIMM1B
P2 DIMM3A
P1 DIMM1A
P2 DIMM3B
CLEAR
VGA
COM1
LAN2
LAN1
USB0/1
CMOS
I-SA
TA
1
JPI2C (PWR I2C)
CPU1
CPU2
BIOS
T-SGPIO1
I-SA
TA
2
I-SA
TA
3
I-SA
TA
4
I-SA
TA
5
I-SA
TA
6
Intel
ICH10R
(South Bridge)
Intel
5520
IOH-36D
Intel
82576
LAN CTRL
Winbond
450R
BMC
P1 DIMM3B
Front Panel CTRL
Battery
X8DTG-DF
J12
JPCIE1
JPCIE2
B
A
A. NMI Header
B. Internal Speaker
Internal Buzzer
The Internal Buzzer, located at JSPK1, can be
used to provide audible alarms for various beep
codes. See the table on the right for pin defi ni-
tions. Refer to the layout below for the locations
of the Internal Speaker/Buzzer.
Internal Buzzer
Pin Defi nitions
Pin# Defi nitions
Pin 1
Pos. (+)
Beep In
Pin 2
Neg. (-)
Alarm Speaker
NMI Header
The non-maskable interrupt header is located
at JNMI1. Refer to the table on the right for
pin defi nitions.
NMI Button
Pin Defi nitions (JF1)
Pin# Defi nition
1
Control
2
Ground
