Supero X10DAC, User Manual

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Chapter 4: AMI BIOS
4-27
Thunderbolt PCIe Cache-line Size
Use this item to set the PCI-E cache-line size to be used in THE Thunderbolt sub-
tree. The options are 0, 1, 2, 4, 8, 16,
32 , 64 and 128.
SMI/Notify Support
If this item is set to Enabled, SMI (Structure of Management Information) notifica -
tion will be provided for Thunderbolt Technology support. The options are Enabled
and
Disabled .
Ignore Thunderbolt Option ROM
Select Enabled to ignore Thunderbolt Option ROM, which will not allow the system
to boot up from a PCI-E device used in the Thunderbolt technology. The options
are
Enabled and Disabled.
Thunderbolt SwSMI Delay
Use this item to set the time delay setting to allow a PCI-E device used in the
Thunderbolt technology to be detected by the BIOS before system boot. The default
setting is
0 (=Disabled) .
TBT Device IO Resource Support
Select Enabled to allocate IO resources to be used by "Thunderbolt devices". The
options are Enabled and Disabled.
Reserved Mem (Memory) per Phy (Physical) Slot
Use this item to specify the size of memory that the BIOS should allocate for each
PCI-E physical slot when the onboard PCI-E devices will consume more than the
total size of memory available on the motherboard. The default setting is
32 .
Reserved PMem (Prefetchable Memory) per Phy (Physical) Slot
Use this item to specify the size of prefetchable memory that the BIOS should al-
locate for each PCI-E physical slot when the onboard PCI-E devices will consume
more than the total size of memory available on the motherboard. The default
setting is
32
.