Supero SUPERSERVER 6113L-8, User Manual

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UPER
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ERVER 6113L-8/6113L-i User's Manual
1-2
1-2 Serverboard Features
At the heart of the SuperServer 6113L-8/6113L-i lies the i2DML-8G2/i2DML-iG2,
a dual Intel Itanium2 processor serverboard designed to provide maximum perfor-
mance. Below are the main features of the i2DML-8G2/i2DML-iG2.
Chipset
The i2DML-8G2/i2DML-iG2 is based on Intel's E8870 chipset, which is a high-
performance chipset designed for high-end server platforms (see Figure 1-1).
The Intel 8870 chipset consists of the four primary components: the Scalable Node
Controller (SNC), the Server I/O Hub (SIOH), the DDR Memory Hub (DMH), and the
Scalability Port Switch (SPS). Complementary components include the I/O Hub
Controller (Intel ICH4), the Firmware Hub (FWH), and the PCI Bus Bridge (P64H2).
The SNC is the main component in the processor/memory subsystem. It con-
nects to four DDR memory hubs through four separate links to provide a peak
memory bandwidth of 6.4 GB/s. Each DDR Memory Hub connects to two branch
channels and supports up to four DDR SDRAM DIMMs per channel. The
Scalability Port (SP) provides simultaneous, bi-directional signaling with an ag-
gregate bandwidth of 6.4 GB/sec per port. Two SP ports per SNC provide a
maximum bandwidth capability of 12.8 GB/s. The SNC delivers balanced, high-
bandwidth throughput across the processors, memory and I/O.
The SIOH is the central component of the I/O subsystem and provides the
connection between four Hub Interface 2.0 ports and two Scalability Ports. The
the SIOH with four Hub Interfaces has a aggregate peak bandwidth of 4 GB/sec.
The SIOH also offers a Hub Interface 1.5 connection to legacy I/O and firmware
via the I/O Controller Hub (ICH4).
The DMH is a bridge for data transfers between the SNC and the two DDR
memory channels. Each DMH has a maximum throughput of 1.6 GB/s and sup-
ports up to eight single or double density registered DIMMs.
The SPS is not used in the i2DML-8G2/i2DML-iG2.
Note: "(B)" indicates black.