Supero 5018A-MLHN4, User Manual

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SUPERSERVER 5018A-MLHN4 User's Manual
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Processor Frequency
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Microcode Revision
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L1 Cache RAM
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L2 L1 Cache RAM
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Processor Version
Clock Spread Spectrum
If this feature is set to Enabled, the BIOS will monitor the level of Electromagnetic
Interference caused by the components and will attempt to reduce the interference
when needed. The options are Enabled and Disabled .
EIST (GV3)
EIST (Enhanced Intel SpeedStep Technology) allows the system to automatically
adjust processor voltage and core frequency in an effort to reduce power consump-
tion and heat dissipation. The options are Disabled, Enabled, and Auto .
P-State Coordination
This feature selects the type of coordination for the P-State of the processor. P-State
is a processor operational state that reduces the processor's voltage and frequency.
This makes the processor more energy effi cient, resulting in further energy gains.
The options are Hardware, Package , and Module.
TM1 (Available when supported by the CPU.)
Select Enabled to activate CPU's internal thermal monitor mechanism which will
allow the CPU to regulate its power consumption based on the modulation of its
internal clock when the CPU temperature reaches a pre-defi ned overheat threshold.
The options are Disabled and Enabled .
TM2 Mode (Available when the item above-TM1 is Enabled)
This feature is used to set the TM2 mode. The options are LFM Throttling, and
Adaptive Throttling .
CPU C State
The CPU C-State architecture is a processor power management platform devel-
oped by Intel to reduce power consumption by blocking clock cycles to the CPU
during C1 State (Halt State). Select Enabled for CPU C-Sates support. The options
are Auto , Enabled, and Disabled.