Chapter 4: BIOS
4-11
X
Advanced Chipset Control
Access the submenu to make changes to the following settings.
*
Warning
: Take Caution when changing the Advanced settings. Incorrect
values entered may cause system malfunction. Also, a very high DRAM
frequency or incorrect DRAM timing may cause system instability. When this
occurs, revert to the default setting.
SERR Signal Condition
This setting specifi es the ECC Error conditions that an SERR# is to be asserted.
The options are None,
Single Bit
, Multiple Bit, and Both.
4GB PCI Hole Granularity
This feature allows you to select the granularity of PCI hole for PCI slots. If MTRRs
are not enough, this option may be used to reduce MTRR occupation. The options
are:
256 MB
, 512 MB, 1GB and 2GB.
Memory Branch Mode
This option determines how the memory branch operates. System address space
can either be interleaved between two channels or Sequential from one channel
to another. Single Channel 0 allows a single DIMM population during system
manufacturing. The options are
Sequential
and Single Channel 0.
Branch 0 Rank Interleaving
Select enable to enable the functions of Memory Interleaving for Branch 0 Rank.
The options for Memory Interleaving are 1:1, 2:1 and
4:1
.
Branch 0 Rank Sparing
Select enable to enable the sparing feature for Branch 0 Rank. The options are
Enabled and
Disabled
.
Enhanced x8 Detection
Select
Enabled
to enable Enhanced x8 DRAM UC Error Detection. The options
are Disabled and
Enabled
.
High Temperature DRAM Operation
When set to
Enabled, BIOS will refer to the SPD table for setting the maximum
DRAM temperature. If disabled, BIOS will set the maximum DRAM temperature
based on a predefi ned value. The options are Enabled and
Disabled
.
AMB Thermal Sensor
Select
Enabled to enable the thermal sensor embedded in the Advanced Memory
Buffer on a fully buffered memory module for thermal monitoring. The options are
Disabled
and Enabled.
