Supermicro X6DH8-XG2, User Manual

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Chapter 1: Introduction
1-9
Introduction
1-2 Chipset Overview
Built upon the functionality and the capability of the E7520 Lindenhurst
chipset, The X6DH8-XG2/X6DHE-XG2 motherboard provides the perfor-
mance and feature set required for dual processor-based servers, with
configuration options optimized for communications, presentation, storage,
computation or database applications. The Intel E7520 Lindenhurst chipset
consists of the following components: the Lindenhurst Memory Controller
Hub (MCH), the 82801ER I/O Controller Hub 5-R (ICH5-R), and the PCI-X Hub.
The E7520 Lindenhurst MCH supports single or dual Nocona processors
with Front Side Bus speeds of up to 800 MHz(*Note). Its memory controller
provides direct connection to two channels of registered DDR2 400 with a
marched system bus address and data bandwidths of up to 6.4GB/s. The
Lindenhurst also supports the new PCI Express high speed serial I/O inter-
face for superior I/O bandwidth. The MCH provides three configurable x8
PCI Express interfaces which may alternatively be configured as two inde-
pendent x4 PCI Express interfaces. These interfaces support connection of
the MCH to a variety of other bridges that are compliant with the PCI Ex-
press Interface Specification, Rev. 1.0a. The MCH interfaces with the
82801ER I/O Controller Hub 5-R (ICH5R) via a dedicated Hub Interface sup-
porting a peak bandwidth of 266 MB/s using a x4 base clock of 66 MHz. The
PXH provides connection between a PCI Express interface and two inde-
pendent PCI bus interfaces that can be configured for standard PCI 2.3
protocol, as well as the enhanced high-frequency PCI-X protocol. The PXH
can be configured to support for 64-bit PCI devices running at 33 MHz, 66
MHz, 100 MHz, and 133 MHz.
The ICH5R I/O Controller Hub provides legacy support similar to that of
previous ICH-family devices, but with extensions in RAID 0,1 support, Serial
ATA Technology, and an integrated ASF Controller. In addition, the ICH5R
also provides various integrated functions, including a two-channel Ultra
ATA/100 bus master IDE controller, USB 2.0 host controllers, an integrated
10/100 LAN controller, an LPC firmware hub (FWH) and Super IO interface,
a System Management Interface, a power management interface, integrated
IOxAPIC and 8259 interrupt controllers.
(*Notes: The CPU FSB speed is set at 800 MHz by the Manufacturer.
Please do not change the CPU FSB setting.)