Super X13SAQ User's Manual
72
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Hyper Threading Technology
•
VMX
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SMX/TXT
•
64-bit
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EIST Technology
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CPU C3 state
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CPU C6 state
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CPU C7 state
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CPU C8 state
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CPU C9 state
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Performance L1 Data Cache
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Performance L1 Instruction Cache
•
Performance L2 Cache
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Performance L3 Cache
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Performance L4 Cache
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Efficient L1 Data Cache
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Efficient L1 Instruction Cache
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Efficient L2 Cache
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Efficient L3 Cache
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Efficient L4 Cache
C6DRAM
Use this feature to enable or disable the moving of DRAM contents to PRM memory when
the CPU is in the C6 state. The options are Disabled and
Enabled
.
