Chapter 4: BIOS
103
Correctable Error Threshold
This feature allows the user to enter the threshold value for correctable memory errors.
The default setting is
512
.
Partial Cache Line Sparing PCLS
Select Enabled to support partial cache line sparing, which will allow partial of data
contained in a cache line to be copied in the cache memory for safe-keeping/data security.
The options are Disabled and
Enabled
.
ADDDC (Adaptive Double Device Data Correction) Sparing (Available if "UEFI ARM
Mirror" is set to Enabled)
Select Enable for Adaptive Double Device Data Correction (ADDDC) support, which will
not only provide memory error checking and correction but will also prevent the system
from issuing a performance penalty before a device fails. Please note that virtual lockstep
mode will only start to work for ADDDC after a faulty DRAM module is spared. The options
are
Enabled
and Disabled.
Patrol Scrub
Patrol Scrubbing is a process that allows the CPU to correct correctable memory errors
detected in a memory module and send the corrections to the requestor (the original
source). When this feature is set to Enable, the IO hub will read and write back one cache
line every 16K cycles if there is no delay caused by internal processing. By using this
method, roughly 64 GB of memory behind the IO hub will be scrubbed every day. The
options are Enabled, Disabled, and
Enable at End of POST
.
IIO Configuration
CPU1 Configuration/CPU2 Configuration
IOU0 (IIO PCIe Port 1)
Use this feature to configure the PCIe Bifurcation setting for a PCIe port specified by the
user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and
Auto
.
IOU1 (IIO PCIe Port 2)
Use this feature to configure the PCIe Bifurcation setting for a PCIe port specified by the
user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and
Auto
.
IOU3 (IIO PCIe Port 4)
Use this feature to configure the PCIe Bifurcation setting for a PCIe port specified by the
user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and
Auto
.
