47
Chapter 2: Installation
BT1
G3
17
1
9
24
16
8
EDP1
44
G9
G11
G7
G1
G8
G10
FAN2
FAN3
FAN1
J3
2
74
75
2
9
2
A17
A19
A18
A1
A2
A4
B1
B2
B19
B20
24
23
25
22
5
2
3
1
4
JBT1
1
5
9
6
18
14
JCOM3
JCOM2
JD1
JGP1
JGP2
JPME2
JPAC1
JI2C2
JI2C1
JWD1
JL1
4
9
5
10
18
19
11
1
LAN1
4
9
5
10
18
23
22
1
LAN2
JPH1
JPT1
JPL2 JPL1
JPW1
12
LED1
A
C
MH4
MH3
MH2
MH1
SRW3
SRW1
SRW2
B12
B1
B11
B2
A1
A12
B12
B1
B11
B2
A1
A12
I-SATA2
I-SATA3
I-SATA4
I-SATA1
I-SATA0
7
JSD1
JPV1
5
4
8
JF1
1
2
19
J11
2
1
J10
2
1
J9
CPU
MAC CODE
BAR CODE
BIOS LICENSE
HD AUDIO
POWER
SATA DOM
SUPERDOM
NON-ECC DDR4 SO-DIMM
CNVi
JMD1 - M.2: PCIE3.0x1
JMD2 - M.2: PCIE3.0x4
USB 6/7 (3.1)
Rev:1.02
DVI-D
COM1/2
1-2:ENABLE
2-3:DISABLE
2-3:DISABLE
1-2:ENABLE
JPL2:LAN2
JPL1:LAN1
20
21
22
23
20
21
19
11
HDMI2.0/DP
COM 3/4
COM 5/6
20
JTPM1
USB 8/9 (3.1)
USB 2/3
USB 0/1
CPU1 SLOT7 PCI-E 3.0x16
10
10
15
DIMMB1
DIMMA1
DESIGNED IN USA
X11SCV-Q
AUDIO FP
LED
PWR
1
LED
HDD
NIC
2
NIC
OH/FF
X RST
ON
JF1
PWR
10
11
USB 4/5 (3.1)
NON-ECC DDR4 SO-DIMM
PCH
1. General Purpose Header 1
2. General Purpose Header 2
General Purpose I/O Header
The JGP1 and JGP2 (General Purpose Input/Output) headers are general purpose I/O
expanders on a pin header via the SMBus. Refer to the tables below for pin definitions.
1
2
JGP1 Header
Pin Definitions
Pin#
Definition PCH Definition Memory Address
1
3.3V
3.3V
2
Ground
Ground
3
GP0
GPP_K20
0xFD6B0740
4
GP1
GPP_K4
0xFD6B0640
5
GP2
GPP_K21
0xFD6B0750
6
GP3
GPP_K5
0xFD6B0650
7
GP4
GPP_K23
0xFD6B0770
8
GP5
GPP_K6
0xFD6B0660
9
GP6
GPP_K3
0xFD6B0630
10
GP7
GPP_K7
0xFD6B0670
JGP2 Header
Pin Definitions
Pin#
Definition PCH Definition Memory Address
1
3.3V
3.3V
2
Ground
Ground
3
GP0
GPP_K8
0xFD6B0680
4
GP1
GPP_K12
0xFD6B06C0
5
GP2
GPP_K9
0xFD6B0690
6
GP3
GPP_K13
0xFD6B06D0
7
GP4
GPP_K10
0xFD6B06A0
8
GP5
GPP_K14
0xFD6B06E0
9
GP6
GPP_K11
0xFD6B06B0
10
GP7
GPP_K15
0xFD6B06F0
