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Sundance Spas SMT364, User Manual

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Sundance Spas SMT364 User Manual Download Page 23

 

 

 

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 

 

At power-up and on reset. 

 
At power-up, the FPGA is not configured and is waiting for a bit stream to be loaded.  
By fitting Jumper J1 (Figure 8 - Connector Location.), it will allow the bit stream 
stored into the PROM to be loaded into the FPGA at power-up and after every TIM 
reset. 
If J1 is not fitted, nothing happens. This condition is useful when needing to configure 
the FPGA via JTAG. 
 
Also at power-up and on a carrier board reset signal, the 

SMT364

 expects receiving 

a dummy ComPort word (any value) and sends one back containing the Firmware 
version number. It is a way of checking that the firmware is latest and that the board 
is responding and ready to work. The format of that ComPort word is as follow: 

0xFF364Fxy

, which means FPGA firmware version 

x

.

y

 

Summary of Contents for SMT364

Page 1: ...User Manual QCF42 Version 3 0 8 11 00 Sundance Multiprocessor Technology Ltd 1999 SMT364 User Manual...

Page 2: ...Version 1 0 Page 2 of 37 SMT364 User Manual Revision History Date Comments Engineer Version 31 07 03 First release PSR 1 0...

Page 3: ...does 9 Ressource occupied 9 ADCs 10 Clock management 10 Sundance High speed Bus SHB 10 Communication Ports ComPorts 11 External triggering 11 LEDs 11 TTL I Os 12 Sundance Standards 12 Communication Po...

Page 4: ...k Diagram 7 Figure 2 FPGA utilisation 9 Figure 3 CommPort interface data path 13 Figure 4 SHB interface structure 13 Figure 5 ADC Performance 15 Figure 6 FFT ADC Channel On board clock 16 Figure 9 SHB...

Page 5: ...the module in a static protective bag during storage and transition The SMT364 reaches a temperature close to the maximum temperature ratings of the ADCs FPGA and DC DC when operated in a closed envi...

Page 6: ...d Bus SHB connectors Four 20 MegaByte s communication ports Low jitter on board system clock Xilinx Virtex II FPGA 50 Ohm terminated analogue inputs and outputs external triggers and clocks via MMBX H...

Page 7: ...bit data ctl 2xAD6645 ADCs C and D 14 bit 105MSPS 52 pin LQFP 2 Clock feedback Trig 1 Trig 2 6 pin JTAG header On board Oscillator 50 MHz 4 LEDs or 4 LVTTL I O pins FPGA PROM XC18V04 Clock Multiplexer...

Page 8: ...linx PROM XC18V04 at startup The default configuration mode is from a PROM which contains the standard modes of operation as described in this document An on board LED indicates that the FPGA is confi...

Page 9: ...h no possible conflict Four control registers are implemented into this FPGA to set up converters their data format clock synthesizers CommPort and SHB Some more details are given in the next parts of...

Page 10: ...SHB Sundance High speed Bus connectors labelled SHBA J2 and SHBB J3 see Figure 8 Connector Location SHBA and SHBB are set as transmitter only to transfer data coming from the Analogue to Digital Conve...

Page 11: ...as active high or low in via the control register Each trigger input is clamped to 3 3 and Ground to avoid damaging the FPGA I Os This is achieved by using single diodes BAV99 These diodes can suppor...

Page 12: ...4 and 5 initialise as receivers When you wire TIMs together you must make sure that you only ever connect links initialising as transmitters to links initialising as receivers never connect two trans...

Page 13: ...re parallel communication links for synchronous transmissions Each SHB can be divided into two independent 8 bit buses Each 8 bit bus includes a clock and three control signals write enable request an...

Page 14: ...364 to be received The board also connects two full SHB connectors 60 bits to the FPGA The FPGA implements two 16 bit or one 32 bit unidirectional transmitter only interfaces per SHB connector to send...

Page 15: ...option 0 320 MHz A to D converters 0 250 MHz External Clock Minimum voltage DC coupled input Requires a External clock signal centered around 0V 0 2 Volt peak to peak minimum Maximum voltage 3 3 Volt...

Page 16: ...second peak due to harmonics at all and with a 35dBc harmonic performance signal generator Figure 6 FFT ADC Channel On board clock Similar results are obtained when using an external clock It is reco...

Page 17: ...29 51 D49 12 D10 ACK0 32 D30 52 D50 13 D11 CLK1 33 D31 53 D51 14 D12 34 D32 WEN2 54 D52 15 D13 35 D33 REQ2 55 D53 16 D14 36 D34 ACK2 56 D54 17 D15 37 D35 CLK3 57 D55 18 D16 38 D36 58 D56 WEN4 19 D17 3...

Page 18: ...the Design ADCD NET adcd_rdy_gclk LOC AB12 NET adcd_rdy LOC AA16 NET adcd_ovr LOC V17 NET adcd_data 13 LOC AB16 NET adcd_data 12 LOC W16 NET adcd_data 11 LOC Y16 NET adcd_data 10 LOC V16 NET adcd_data...

Page 19: ...Y5 NET adca_data 9 LOC W5 NET adca_data 8 LOC V7 NET adca_data 7 LOC V6 NET adca_data 6 LOC AB5 NET adca_data 5 LOC AA5 NET adca_data 4 LOC Y6 NET adca_data 3 LOC W6 NET adca_data 2 LOC AB6 NET adca_d...

Page 20: ...data 1 LOC D9 NET cp4_data 0 LOC C9 NET cp4_ack LOC C7 COMMPORT 3 NET cp3_stb LOC V19 NET cp3_req LOC V22 NET cp3_rdy LOC V20 NET cp3_data 7 LOC T20 NET cp3_data 6 LOC T19 NET cp3_data 5 LOC U22 NET c...

Page 21: ...ba 39 LOC M3 NET shba 38 LOC M2 NET shba 37 LOC M1 NET shba 36 LOC L2 NET shba 35 LOC L3 NET shba 34 LOC L4 NET shba 33 LOC L5 NET shba 32 LOC K1 NET shba 31 LOC K2 NET shba 30 LOC K3 NET shba 29 LOC...

Page 22: ...37 LOC M21 NET shbb 36 LOC L22 NET shbb 35 LOC L21 NET shbb 34 LOC L20 NET shbb 33 LOC L19 NET shbb 32 LOC L18 NET shbb 31 LOC L17 NET shbb 30 LOC K22 NET shbb 29 LOC K21 NET shbb 28 LOC K20 NET shbb...

Page 23: ...GA at power up and after every TIM reset If J1 is not fitted nothing happens This condition is useful when needing to configure the FPGA via JTAG Also at power up and on a carrier board reset signal t...

Page 24: ...Version 1 0 Page 24 of 37 SMT364 User Manual Connector position Figure 8 Connector Location...

Page 25: ...3v power source In addition to the 5v supply specified in the TIM specification these new generation modules require an additional 3 3v supply to be presented on the two diagonally opposite TIM mounti...

Page 26: ...Version 1 0 Page 26 of 37 SMT364 User Manual Register settings Register 0x0 Clock management...

Page 27: ...thesizer M Bit8 ADC CD Bit 19 Clock synthesizer M Bit7 ADC CD Bit 18 Clock synthesizer M Bit6 ADC CD Bit 17 Clock synthesizer M Bit5 ADC CD Bit 16 Clock synthesizer M Bit4 ADC CD Bit 15 Clock synthesi...

Page 28: ...in LQFP 30 I O pins 28 bit data ctl 4 3 RF transformer 2 Clock feedbacks Clk 1 opamp opamp Clock synthe sizer ADCA B Clk 2 AC or DC coupling ADC A ADC B Clock synthe sizer ADCC D Bit25 0 1 Bit24 0 1 0...

Page 29: ...28 1 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22 Bit 21 Bit 20 Bit 17 19 Bit 16 Bit 15 Bit 14 Route D Bit 13 Route C Bit 1 Bit 12 Route C Bit 0 Bit 11 Route B Bit 1 Bit 10 Route B Bit 0 Bit 9 Bit 8 Rout...

Page 30: ...gram shows all the possibilities Data go through a pipeline and can be added with each other Pipe Pipe Pipe Pipe Pipe Pipe Pipe Pipe Pipe Pipe Pipe Pipe Pipe Pipe Pipe Pipe Pipe Pipe Channel A Channel...

Page 31: ...tor Channel D Bit 7 Bit 18 Decimation Factor Channel D Bit 6 Bit 17 Decimation Factor Channel D Bit 5 Bit 16 Decimation Factor Channel D Bit 4 Bit 15 Decimation Factor Channel D Bit 3 Bit 14 Decimatio...

Page 32: ...rough as ADCs output samples in two s complement 14 bit format 14 bit samples coming from the ADC are extended to 16 bit on SHBA Bit13 is copied onto Bits14 and 15 11 Channel A binary encoding Binary...

Page 33: ...tor Channel B Bit 7 Bit 18 Decimation Factor Channel B Bit 6 Bit 17 Decimation Factor Channel B Bit 5 Bit 16 Decimation Factor Channel B Bit 4 Bit 15 Decimation Factor Channel B Bit 3 Bit 14 Decimatio...

Page 34: ...rough as ADCs output samples in two s complement 14 bit format 14 bit samples coming from the ADC are extended to 16 bit on SHBA Bit13 is copied onto Bits14 and 15 11 Channel A binary encoding Binary...

Page 35: ...d in the FPGA including CommPort interface It is note recommended to proceed to an FPGA global reset while communications are happening It might stick the other end into an unknown state After a Reset...

Page 36: ...Serial Interfaces load The clock synthesizers have all a Serial Port Interface By sending this control word the FPGA serialises Register 0x0 and sends it to both clock synthesizers Bit number Descript...

Page 37: ...User Manual SMT364 package The SMT364 comes with an install package SMT6600 that contain examples and a C header file When ordered with either an SMT365 or SMT365E or SMT374 it comes with a Pegasus a...

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