Version 1.1
Page 17 of 24
SMT351 User Manual
FPGA implementation
This section gives some technical details about the FPGA firmware.
Language
Sundance uses Aldec Active-HDL tool for the design entry and the simulation.
The FPGA is fully designed in VHDL.
Synthesis and Implementation tool
The design is implemented using Xilinx ISE 6.1 SP3 and synthesized with XST.
FPGA resource usage
Follow is the device utilization summary after Place and Route:
Resource
XC2VP7
Number of
External IOBs
68% (272 / 396)
Number of
RAMB16s
27% (12 / 44)
Number of
SLICEs
56% (2784 / 4928)
Number of
BUFGMUXs
68% (11 / 16)
Number of
DCMs
100% (4 / 4)
Power PC
0% (1 / 1)
Summary of Contents for SMT351
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