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Sundance Spas SMT332, User Manual

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Sundance Spas SMT332 User Manual Download Page 13

Version 1.3 

Page 13 of 36

 

SMT332/372 User Manual 

 

 

Address (hex) 

Function 

 

0158 0000 

Interrupt control register B - ICRB (write only) 

 

Interrupt Control Register Bit 

Function 

 

8 

Clear to enable FIFO Channel A, flag to INT4. 
Set to enable CINT4 to INT4. 

9 

Clear to enable FIFO Channel A, flag to INT5. 
Set to enable CINT5 to INT5. 

10 

Clear to enable FIFO Channel B, flag to INT6. 
Set to enable CINT6 to INT6. 

11 

Clear to enable FIFO Channel B,  flag to INT7. 
Set to enable CINT7 to INT7. 

13 & 12 

Channel A FIFO flag control. 
00: select empty flag 
01: select almost empty flag 
10: select almost full flag 
11: select full flag 

15 & 14 

Channel B FIFO flag control. 
00: select empty flag 
01: select almost empty flag 
10: select almost full flag 
11: select full flag 

 

Note: Channel A/B relates to the 2 FIFO devices. Refer to the 

FIFO

 section for further 

details. 

Summary of Contents for SMT332

Page 1: ...User Manual QCF42 Version 3 0 8 11 00 Sundance Multiprocessor Technology Ltd 1999 SMT332 372 User Manual...

Page 2: ...evision History Date Comments Engineer Version 7 3 00 Original Revision GP 1 1 9 3 00 General reorganisation GP 1 2 14 08 00 Comport data rate safe mode not working and samples code using DMA AN 1 3 2...

Page 3: ...features SMT332 TMS320C6201 processor running at 200MHz SMT372 TMS320C6701 processor running at 166MHz Four communications ports approx 15M bytes s 512k bytes of fast SBSRAM 16M bytes SDRAM 256k byte...

Page 4: ...ode 7 EMIF Control Registers 8 SBSRAM 8 SDRAM 8 Flash 9 Comm ports 9 Interrupts 11 NMI 15 IACK 15 CONFIG 15 FIFO Data Input Output 16 Global Expansion 18 Clock Speed 19 Memory Map MAP 1 20 Example Cod...

Page 5: ...Version 1 3 Page 5 of 36 SMT332 372 User Manual Serial Ports 35 FPGA Configuration 36...

Page 6: ...rt Architecture Description The SMT332 TIM consists of a Texas Instruments TMS320C6201 running at 200MHz and the SMT372 has a TMS320C6701 running at 166MHz The TIM is populated with 512k bytes of SBSR...

Page 7: ...en configured This is provided by a control register accessible by the C6x01 Boot Mode The C6x01 is capable of booting in several different modes On the SMT332 372 the boot mode is defined such that t...

Page 8: ...mings CE2 0x00000030 Indicates SDRAM CE3 0x00000030 0xFFFF3F23 Defines SDRAM timings for access to the FIFO data Defines async memory timings for access to FIFO flag programming SBSRAM Connected to th...

Page 9: ...m ports on the SMT332 372 will interface to any standard C4x comm port The comm ports can operate in two modes The first mode is for the C6x01 to transfer data to the port directly using a polling tec...

Page 10: ...x buffer empty 2 Comm port 3 rx data available 3 Comm port 3 tx buffer empty 4 Comm port 1 rx data available 5 Comm port 1 tx buffer empty 6 Comm port 4 rx data available 7 Comm port 4 tx buffer empty...

Page 11: ...Y signals on the comm port Slow interrupts are generated when the fourth STRB of a word transfer goes high At some point after this the C6x01 External Memory Interface strobe nCE1 becomes active Howev...

Page 12: ...rx data available to INT7 01 Enable Comm Port 4 tx data available to INT7 10 Enable IIOF0 to INT7 11 Enable IIOF2 to INT7 8 0 Comm Port 0 rx slow 1 Comm Port 0 rx fast 9 0 Comm Port 0 tx slow 1 Comm P...

Page 13: ...INT5 10 Clear to enable FIFO Channel B flag to INT6 Set to enable CINT6 to INT6 11 Clear to enable FIFO Channel B flag to INT7 Set to enable CINT7 to INT7 13 12 Channel A FIFO flag control 00 select e...

Page 14: ...Version 1 3 Page 14 of 36 SMT332 372 User Manual The functions of ICRA and ICRB are shown diagrammatically below 0 1 1 0 1 0 0 1 ICRB8 ICRB9 ICRB10 ICRB11 ICRB13 12 ICRB15 14...

Page 15: ...ernal Memory Interface register settings for memory space CE1 With the default timings this pulse will be 40ns CONFIG The TIM specification describes the operation of an open collector type signal CON...

Page 16: ...see Interrupts The pin allocation for the I O connectors is shown in Appendix The control signals are derived from the FIFO requirements that may be seen in the appropriate data sheet The device used...

Page 17: ...00C000 And finally the memory needs to be defined as SDRAM For convenience C source code routines for performing these function are included on the distribution disc FIFO Status The FIFO status can be...

Page 18: ...bus transactions are synchronised to the C6x01 clock speed The global bus may be accessed directly by the C6x01 via this EPLD where it may perform reads or writes A maximum block size of 64k words ca...

Page 19: ...he following table shows all available possibilities Device Comment C6x01 SBSRAM SDRAM 133 133 67 Zero wait state SBSRAM 166 166 83 Zero wait state SBSRAM 200 100 100 One wait state SBSRAM 200 200 100...

Page 20: ...rrupt Control Register B ICRB RD FIFO Flag Status Comm Ports 0160 0000 External Memory Space CE1 FPGA internal registers Comm ports Comm Ports 0170 0000 External Memory Space CE1 Global bus access Glo...

Page 21: ...C6x01 internal EMIFCE3 control register at address 0x01800014 and sets it to async mode EMIF_CE3_CTRL 0xffff3f23 To reset the FIFOs including flag positions just write to address 0x03004000 The value...

Page 22: ...is is needed to program the FIFO offsets make a copy of the current EMIF CE3 mode old_ce3 EMIF_CE3_CTRL This writes to the C6x01 internal EMIFCE3 control register at address 0x01800014 and sets it to...

Page 23: ...0014 ICRB 0x01580000 SMT332INTCTRLA 0x00 FIFOA full INT4 FIFOB full INT5 SMT332INTCTRLB 0xF000 Setup the DMA channel to read the FIFO DMA Priority CPU no TCINTerrupt INCrement destination address only...

Page 24: ...rnal data memory into external SDRAM DMA_PRI_CRTL0 0x01000050 DMA_SRC_ADDR0 unsigned int 0x80008000 SDRAM is at address 0x02000000 DMA_DST_ADDR0 unsigned int 0x02000000 j 0x00008000 DMA_XFR_CNTR0 0x00...

Page 25: ...ings emif_ce1 unsigned 0x01800004 emif_ce1 0x8238c823 If we stick a little ramp into SBSRAM and use this as the source of our DMA then we get a pretty result Make sure you don t overwrite the program...

Page 26: ...different from PC to PC In this case it is at address 0xFE000000 global unsigned 0x01700000 global 0xfe000000 blocks 0x8000 Back to the page register and point to the SMT320 FIFO This is where reads...

Page 27: ...000 DMA_SRC_ADDR0 unsigned int SMT331COMMPORT1 DMA_DST_ADDR0 unsigned int SDRAM0 DMA_XFR_CNTR0 N_FRAME 16 FRAME_SIZE DMA_GL_CNT_RLD FRAME_SIZE DMA_GL_INDEX 0x00040004 TIMER0_PERIOD 0xffffffff DMA_SEC_...

Page 28: ...0x0004 Slow mode Comport3 TX data to INT5 DMA_PRI_CTRL0 0x01280030 DMA_SEC_CTRL0 0x00006000 Set WSYNC STAT Clear RSYNC STAT DMA_SRC_ADDR0 unsigned int SDRAM0 DMA_DST_ADDR0 unsigned int SMT331COMMPORT3...

Page 29: ...000 Server Loader and the associated library The Server Loader is an application which runs on a host PC under either Windows 98 or NT It allows applications in the standard TI COFF format to be downl...

Page 30: ...Version 1 3 Page 30 of 36 SMT332 372 User Manual Mechanical Configuration...

Page 31: ...er board The SMT332 372 TIM is in a range of modules which must be supplied with a 3 3v power source In addition to the 5v supply specified in the TIM specification these new generation modules requir...

Page 32: ...36 SMT332 372 User Manual Connectors Tim Connector Position The following drawings illustrate the respective positions of the TIM connectors and the FIFO data optional connector PRIMARY CONNECTOR MOTH...

Page 33: ...2 GND 30 29 DIN13 GND 32 31 DIN14 GND 34 33 DIN15 GND 36 35 FLAG GND 38 37 WEN GND 40 39 RESET The SMT332 372 has two SDB connectors FIFO channel A uses connector labelled HDR1 and channel B uses HDR2...

Page 34: ...9 DIN8A GND 22 21 DIN9A GND 24 23 DIN10A GND 26 25 DIN11A GND 28 27 DIN12A GND 30 29 DIN13A GND 32 31 DIN14A GND 34 33 DIN15A GND 36 35 FLAGA GND 38 37 WENA GND 40 39 RESETA GND 42 41 WCLKB GND 44 43...

Page 35: ...Socket on Carrier FX4C 80S 1 27DSA TIM site Socket on Carrier FX4C1 80S 1 27DSA Serial Ports The C6x contains two multi channel buffered serial ports McBSP The signals involved are connected to a 0 1...

Page 36: ...ister Bit Function 8 Set to assert the PROG pin to the FPGA After the PROG pin has been cycled high and low the FPGA must have its configuration file loaded a byte at a time using the Comm port contro...

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