Sun Microsystems SUN BLADE 150, Service Manual

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Appendix C Functional Description C-25
C.11 Interrupts
C.11.1 Interrupt Interface
The CPU uses a 6-bit encoded interrupt vector mechanism. An IChip2 is used as an
interrupt concentrator, which receives all the system interrupts and encodes the
interrupts into a 6-bit interrupt vector. The interrupt vector is then registered and
synchronized externally with PCI clock before sending to the processor. The
difference between the IChip and IChip2 is the package. IChip is a 120p-pin MQFP
and IChip2 is a 128-pin TQFP.
C.12 Power
The Sun Blade 150 system is Energy Star compliant.
The Sun Blade 150 uses the Tier2, Guideline B of the EPA 3.0 MOU. This means that
when Sun Blade 150 is in a power managed state the maximum power consumption
is 37.5 Watts or less.
When put into Energy Star mode, the UltraSPARC IIi processor reduces the core
clock speed by dividing the input clock by a factor of six internally. The PCI clocks
to the PCI slots are stopped. The peripheral compliance I/O-2 (PCIO-2.x) keeps
running at full PCI speed to support “network awareness.” The SDRAM is put into
the self-refresh mode and will only come out to complete a transaction. If the
SDRAM is in self-refresh mode and there is a pending transaction, the CPU takes the
SDRAM out of self-refresh mode. Upon completion of the transaction and if the
software has not changed the SDRAM self-refresh bit, the CPU (hardware) puts the
SDRAM back into self refresh.
C.12.1 Energy Star
The Sun Blade 150 motherboard follows the guidelines set up by the U.S. EPA’s
Energy Star program. The current MOU is revision 3.0. Refer to:
http://www.epa.gov/appdstar/esoe/moureq.html
The current Energy Star requirement for computers with power supplies that are
from 0 to 250W is 37.5W when in power-saving mode.