STMicroelectronics STM32L151QCH6 Manual Download Page 97

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DocID026119 Rev 5

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STM32L151xC/C-A STM32L152xC/C-A

Electrical characteristics

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Figure 21. SPI timing diagram - slave mode and CPHA = 0

Figure 22. SPI timing diagram - slave mode and CPHA = 1

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Summary of Contents for STM32L151QCH6

Page 1: ...kHz to 4 2 MHz PLL for CPU clock and USB 48 MHz Pre programmed bootloader USB and USART supported Serial wire debug JTAG and trace Up to 116 fast I Os 102 I Os 5V tolerant all mappable on 16 external...

Page 2: ...19 3 3 2 Power supply supervisor 19 3 3 3 Voltage regulator 20 3 3 4 Boot modes 20 3 4 Clock management 21 3 5 Low power real time clock and backup registers 23 3 6 GPIOs general purpose inputs outpu...

Page 3: ...USB 30 3 18 CRC cyclic redundancy check calculation unit 30 3 19 Development support 31 3 19 1 Serial wire JTAG debug port SWJ DP 31 3 19 2 Embedded Trace Macrocell 31 4 Pin descriptions 32 5 Memory...

Page 4: ...cations interfaces 94 6 3 17 12 bit ADC characteristics 102 6 3 18 DAC electrical specifications 107 6 3 19 Operational amplifier characteristics 109 6 3 20 Temperature sensor characteristics 111 6 3...

Page 5: ...cessing running from RAM 65 Table 19 Current consumption in Sleep mode 66 Table 20 Current consumption in Low power run mode 67 Table 21 Current consumption in Low power sleep mode 68 Table 22 Typical...

Page 6: ...111 Table 61 Temperature sensor characteristics 111 Table 62 Comparator 1 characteristics 111 Table 63 Comparator 2 characteristics 112 Table 64 LCD controller characteristics 113 Table 65 LQFP144 20...

Page 7: ...I2 S slave timing diagram Philips protocol 1 101 Figure 26 I2 S master timing diagram Philips protocol 1 101 Figure 27 ADC accuracy characteristics 105 Figure 28 Typical connection diagram using the...

Page 8: ...5 Figure 43 WLCSP64 0 400 mm pitch package outline 126 Figure 44 WLCSP64 0 400 mm pitch package recommended footprint 127 Figure 45 WLCSP64 0 400 mm pitch package top view example 128 Figure 46 Therm...

Page 9: ...s family These features make the ultra low power STM32L151xC C A and STM32L152xC C A microcontroller family suitable for a wide range of applications Medical and handheld equipment Application control...

Page 10: ...the STM32L151xC C A and STM32L152xC C A devices contain standard and advanced communication interfaces up to two I2Cs three SPIs two I2S three USARTs and an USB The STM32L151xC C A and STM32L152xC C A...

Page 11: ...3 2 I2 C 2 USART 3 USB 1 GPIOs 51 83 109 115 Operation amplifiers 2 12 bit synchronized ADC Number of channels 1 21 1 25 1 40 1 40 12 bit DAC Number of channels 2 2 LCD STM32L152xx devices only COM x...

Page 12: ...orate highly energy efficient cores with both Harvard architecture and pipelined execution advanced STM8 core for STM8L families and ARM Cortex M3 core for STM32L family In addition specific care for...

Page 13: ...3257 5 6 3 2 3257 3 2 3257 7 0 56 ELWV ELW 63 6 75 75 75 75 75 6 VWHP DS VHQV 6XSSO PRQLWRULQJ 9 9 9 9 6XSSO PRQLWRULQJ DS VHQVLQJ 3 2 3257 3 2 3257 3 PD 0 3 PD 0 3 ORFN 0JPW 9 13 9 10 9287 9 13 9 10...

Page 14: ...MSI RC oscillator set to the minimum clock 131 kHz execution from SRAM or Flash memory and internal regulator in low power mode to minimize the regulator s operating current In low power run mode the...

Page 15: ...ising edge on one of the three WKUP pins RTC alarm Alarm A or Alarm B RTC tamper event RTC timestamp event or RTC Wakeup event occurs Standby mode without RTC Standby mode is used to achieve the lowes...

Page 16: ...es For example to switch from 4 2 MHz to 32 MHz you can switch from 4 2 MHz to 16 MHz wait 5 s then switch from 16 MHz to 32 MHz 2 Should be USB compliant from I O voltage standpoint the minimum VDD i...

Page 17: ...Y Y Y Y Y Y EEPROM Y Y Y Y Y Brown out rest BOR Y Y Y Y Y Y Y DMA Y Y Y Y Programmable Voltage Detector PVD Y Y Y Y Y Y Y Power On Reset POR Y Y Y Y Y Y Y Power Down Rest PDR Y Y Y Y Y Y High Speed In...

Page 18: ...Y Y Y Y Y OP amp Y Y Y Y Y Comparators Y Y Y Y Y Y 16 bit and 32 bit Timers Y Y Y Y IWDG Y Y Y Y Y Y Y Y WWDG Y Y Y Y Touch sensing Y Y Systic Timer Y Y Y Y GPIOs Y Y Y Y Y Y 3 pins Wakeup time to Run...

Page 19: ...is hardware block provides flexible interrupt management features with minimal interrupt latency 3 3 Reset and supply management 3 3 1 Power supply schemes VDD 1 65 to 3 6 V external power supply for...

Page 20: ...hosen by software with a step around 200 mV An interrupt can be generated when VDD VDDA drops below the VPVD threshold and or when VDD VDDA is higher than the VPVD threshold The interrupt service rout...

Page 21: ...E the MSI frequency can be trimmed by software down to a 0 5 accuracy Auxiliary clock source two ultra low power clock sources that can be used to drive the LCD controller and the real time clock 32 7...

Page 22: ...NTROL LOCK 7ATCHDOG ENABLE 24 ENABLE CK HSI CK HSE 3 PRESENT OR NOT 3 TEMPO CK PLL PRESCALER 0 0 CK USB 6CO 6CO MUST BE AT Z 4 393 05 072 53 4 4 0 0 USBEN AND NOT DEEPSLEEP TIMER EN AND NOT DEEPSLEEP...

Page 23: ...hese pins can reset backup register and generate an interrupt To prevent false tamper event like ESD event these three tamper inputs can be digitally filtered 3 6 GPIOs general purpose inputs outputs...

Page 24: ...3 8 DMA direct memory access The flexible 12 channel general purpose DMA is able to manage memory to memory peripheral to memory and memory to peripheral transfers The DMA controller supports circular...

Page 25: ...e MCU operating mode 3 10 1 Temperature sensor The temperature sensor TS generates a voltage VSENSE that varies linearly with temperature The temperature sensor is internally connected to the ADC_IN16...

Page 26: ...and STM32L152xC C A devices The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels 3 12 Operational amplifier The STM32L151xC C A and STM32L...

Page 27: ...th software and timer capacitive sensing acquisition modes are supported Capacitive sensing technology is able to detect the presence of a finger near a sensor which is protected from direct touch by...

Page 28: ...ration These timers are capable of handling quadrature incremental encoder signals and the digital outputs from 1 to 3 hall effect sensors TIM10 TIM11 and TIM9 TIM10 and TIM11 are based on a 16 bit au...

Page 29: ...s free running It can be used as a watchdog to reset the device when a problem occurs It is clocked from the main clock It has an early warning interrupt capability and the counter can be frozen in de...

Page 30: ...ces embed a USB device peripheral compatible with the USB full speed 12 Mbit s The USB interface implements a full speed 12 Mbit s function interface It has software configurable endpoint setting and...

Page 31: ...d with a JTAG fuse 3 19 2 Embedded Trace Macrocell The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a...

Page 32: ...op view 3 6 6 6 33 0 0 0 0 4 0 0 0 0 0 0 6 6 33 0 0 0 0 0 0 0 0 6 6 33 0 0 0 0 0 0 0 0 0 0 0 0 6 0 633 0 0 0 0 7 50 0 0 0 7 50 0 0 3 0 0 3 54 0 0 0 0 0 0 0 0 0 0 6 0 633 633 0 6 0 0 0 0 0 0 0 0 0 0 0...

Page 33: ...kage top view 3 6 0 0 3 54 0 3 0 0 0 0 0 0 7 50 6 633 6 234 0 0 0 633 0 0 6 4 0 633 0 0 0 0 0 0 0 0 0 0 0 0 7 50 0 3 0 3 54 6 6 0 0 633 633 0 0 0 0 0 0 0 0 0 633 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0...

Page 34: ...0 pinout 1 This figure shows the package top view 6 633 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 633 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 633 6 6 633 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 35: ...criptions 54 Figure 6 STM32L15xRC A LQFP64 pinout 1 This figure shows the package top view 6 0 7 50 0 3 0 3 54 0 3 0 3 54 234 0 0 0 0 633 6 0 7 50 0 0 6 633 0 0 4 0 0 0 0 0 0 0 0 0 0 0 6 633 0 0 0 0 0...

Page 36: ...brackets below the pin name the pin function during and after reset is the same as the actual pin name Pin type S Supply pin I Input only pin I O Input output pin I O structure FT 5 V tolerant I O TC...

Page 37: ...definitions Pins Pin name Pin Type 1 I O structure Main function 2 after reset Pin functions LQFP144 UFBGA132 LQFP100 LQFP64 WLCSP64 Alternate functions Additional functions 1 B2 1 PE2 I O FT PE2 TIM...

Page 38: ...H0 OSC_IN 24 G1 13 6 D7 PH1 OSC_OUT 5 I O TC PH1 OSC_OUT 25 H2 14 7 C7 NRST I O RST NRST 26 H1 15 8 E8 PC0 I O FT PC0 LCD_SEG18 ADC_IN10 COMP1_INP 27 J2 16 9 F8 PC1 I O FT PC1 LCD_SEG19 ADC_IN11 COMP1...

Page 39: ...INM 37 L3 26 17 G7 PA3 I O TC PA3 TIM2_CH4 TIM5_CH4 TIM9_CH2 USART2_RX LCD_SEG2 ADC_IN3 COMP1_INP OPAMP1_VOUT 38 27 18 F5 VSS_4 S VSS_4 39 28 19 G6 VDD_4 S VDD_4 40 J4 29 20 H7 PA4 I O TC PA4 SPI1_NSS...

Page 40: ...9 COMP1_INP VREF_OUT 37 28 H3 PB2 I O FT PB2 BOOT1 BOOT1 COMP1_INP 48 L6 PB2 I O FT PB2 BOOT1 BOOT1 ADC_IN0b COMP1_INP 49 K6 PF11 I O FT PF11 ADC_IN1b COMP1_INP 50 J7 PF12 I O FT PF12 ADC_IN2b COMP1_I...

Page 41: ...SPI1_MISO 68 M12 46 PE15 I O FT PE15 SPI1_MOSI 69 L10 47 29 G3 PB10 I O FT PB10 TIM2_CH3 I2C2_SCL USART3_TX LCD_SEG10 70 L11 48 30 F3 PB11 I O FT PB11 TIM2_CH4 I2C2_SDA USART3_RX LCD_SEG11 71 F12 49 3...

Page 42: ...2 82 H12 60 PD13 I O FT PD13 TIM4_CH2 LCD_SEG33 83 VSS_8 S VSS_8 84 VDD_8 S VDD_8 85 H11 61 PD14 I O FT PD14 TIM4_CH3 LCD_SEG34 86 H10 62 PD15 I O FT PD15 TIM4_CH4 LCD_SEG35 87 G10 PG2 I O FT PG2 ADC_...

Page 43: ...T JTMS SWDIO JTMS SWDIO 106 C11 73 PH2 I O FT PH2 107 F11 74 47 B1 VSS_2 S VSS_2 108 G11 75 48 A1 VDD_2 S VDD_2 109 A10 76 49 B2 PA14 I O FT JTCK SWCLK JTCK SWCLK 110 A9 77 50 C3 PA15 I O FT JTDI TIM2...

Page 44: ...3 A5 88 PD7 I O FT PD7 TIM9_CH2 USART2_CK 124 D9 PG9 I O FT PG9 125 D8 PG10 I O FT PG10 126 PG11 I O FT PG11 127 D7 PG12 I O FT PG12 128 C7 PG13 I O FT PG13 129 C6 PG14 I O FT PG14 130 VSS_11 S VSS_11...

Page 45: ...igured as OSC32_IN OSC32_OUT when the LSE oscillator is ON by setting the LSEON bit in the RCC_CSR register The LSE oscillator pins OSC32_IN OSC32_OUT can be used as general purpose PH0 PH1 I Os respe...

Page 46: ...TIM5_CH1 USART2_CTS TIMx_IC1 EVENT OUT PA1 TIM2_CH2 TIM5_CH2 USART2_RTS SEG0 TIMx_IC2 EVENT OUT PA2 TIM2_CH3 TIM5_CH3 TIM9_CH1 USART2_TX SEG1 TIMx_IC3 EVENT OUT PA3 TIM2_CH4 TIM5_CH4 TIM9_CH2 USART2_...

Page 47: ...IM3_CH1 SPI1_MISO SPI3_MISO SEG8 EVENT OUT PB5 TIM3_CH2 I2C1_ SMBA SPI1_MOSI SPI3_MOSI I2S3_SD SEG9 EVENT OUT PB6 TIM4_CH1 I2C1_SCL USART1_TX EVENT OUT PB7 TIM4_CH2 I2C1_SDA USART1_RX EVENT OUT PB8 TI...

Page 48: ...EG19 TIMx_IC2 EVENT OUT PC2 SEG20 TIMx_IC3 EVENT OUT PC3 SEG21 TIMx_IC4 EVENT OUT PC4 SEG22 TIMx_IC1 EVENT OUT PC5 SEG23 TIMx_IC2 EVENT OUT PC6 TIM3_CH1 I2S2_MCK SEG24 TIMx_IC3 EVENT OUT PC7 TIM3_CH2...

Page 49: ...2S2_WS TIMx_IC1 EVENT OUT PD1 SPI2 SCK I2S2_CK TIMx_IC2 EVENT OUT PD2 TIM3_ETR COM7 SEG31 SEG43 TIMx_IC3 EVENT OUT PD3 SPI2_MISO USART2_CTS TIMx_IC4 EVENT OUT PD4 SPI2_MOSI I2S2_SD USART2_RTS TIMx_IC1...

Page 50: ...EVENT OUT PE0 TIM4_ETR TIM10_CH1 SEG36 TIMx_IC1 EVENT OUT PE1 TIM11_CH1 SEG37 TIMx_IC2 EVENT OUT PE2 TRACECK TIM3_ETR SEG 38 TIMx_IC3 EVENT OUT PE3 TRACED0 TIM3_CH1 SEG 39 TIMx_IC4 EVENT OUT PE4 TRACE...

Page 51: ...UT PE13 SPI1_SCK TIMx_IC2 EVENT OUT PE14 SPI1_MISO TIMx_IC3 EVENT OUT PE15 SPI1_MOSI TIMx_IC4 EVENT OUT PF0 EVENT OUT PF1 EVENT OUT PF2 EVENT OUT PF3 EVENT OUT PF4 EVENT OUT PF5 EVENT OUT Table 9 Alte...

Page 52: ...2 EVENT OUT PF13 EVENT OUT PF14 EVENT OUT PF15 EVENT OUT PG0 EVENT OUT PG1 EVENT OUT PG2 EVENT OUT PG3 EVENT OUT PG4 EVENT OUT Table 9 Alternate function input output continued Port name Digital alter...

Page 53: ...ENT OUT PG12 EVENT OUT PG13 EVENT OUT PG14 EVENT OUT PG15 EVENT OUT PH0OSC_IN PH1OSC_OUT PH2 Table 9 Alternate function input output continued Port name Digital alternate function number AFIO0 AFIO1 A...

Page 54: ...IPHERALS 32 O RTEX NTERNAL 0ERIPHERALS 3 6 BYTE 53 4 4 4 X X X X X 0ORT 0ORT 0ORT 0ORT 0ORT 0ORT X X X X X X 0 2 LASH MEMORY 3YSTEM MEMORY LIASED TO LASH OR SYSTEM MEMORY DEPENDING ON 4 PINS ATA 02 RE...

Page 55: ...to sample tests and represent the mean value plus or minus three times the standard deviation mean 3 6 1 2 Typical values Unless otherwise specified typical data are based on TA 25 C VDD 3 6 V for th...

Page 56: ...119 Rev 5 6 1 6 Power supply scheme Figure 11 Power supply scheme 06 9 QDORJ 26 3 203 9 3 2V 287 1 HUQHO ORJLF 38 LJLWDO 0HPRULHV 6WDQGE SRZHU FLUFXLWU 6 57 DNH XS ORJLF 57 EDFNXS UHJLVWHUV 1 Q 5HJXOD...

Page 57: ...by a dedicated VLCD supply source VSEL switch is open 2 Option 2 LCD power supply is provided by the internal step up converter VSEL switch is closed an external capacitance is needed for correct beh...

Page 58: ...rrent values Table 11 Current characteristics Symbol Ratings Max Unit IVDD Total current into sum of all VDD_x power lines source 1 100 mA IVSS 2 Total current out of sum of all VSS_x ground lines sin...

Page 59: ...mbol Parameter Conditions Min Max Unit fHCLK Internal AHB clock frequency 0 32 MHz fPCLK1 Internal APB1 clock frequency 0 32 fPCLK2 Internal APB2 clock frequency 0 32 VDD Standard operating voltage BO...

Page 60: ...29 5 In low power dissipation state TA can be extended to 40 C to 105 C temperature range as long as TJ does not exceed TJ max see Table 71 Thermal characteristics on page 129 Table 13 General operati...

Page 61: ...34 2 38 VPVD3 PVD threshold 3 Falling edge 2 39 2 44 2 48 Rising edge 2 47 2 54 2 58 VPVD4 PVD threshold 4 Falling edge 2 57 2 64 2 69 Rising edge 2 68 2 74 2 79 VPVD5 PVD threshold 5 Falling edge 2 7...

Page 62: ...ding uncertainties due to ADC and VDDA VREF values 5 mV TCoeff 3 Temperature coefficient 40 C TJ 110 C 20 50 ppm C 0 C TJ 50 C 20 ACoeff 3 Long term stability 1000 hours T 25 C 1000 ppm VDDCoeff 3 Vol...

Page 63: ...25 C and VDD supply voltage conditions summarized in Table 13 General operating conditions unless otherwise specified The MCU is placed under the following conditions All I O pins are configured in an...

Page 64: ...e3 VCORE 1 2 V VOS 1 0 11 1 290 500 A 2 505 750 4 955 1200 Range2 VCORE 1 5 V VOS 1 0 10 4 1 15 1 6 mA 8 2 3 2 9 16 4 25 5 2 Range1 VCORE 1 8 V VOS 1 0 01 8 2 65 3 5 16 5 35 6 5 32 10 5 12 HSI clock s...

Page 65: ...ed fHSE fHCLK 2 above 16MHz PLL ON 1 Range3 VCORE 1 2 V VOS 1 0 11 1 230 470 A 2 415 780 4 800 1200 Range2 VCORE 1 5 V VOS 1 0 10 4 0 935 1 5 mA 8 1 9 3 16 3 75 5 Range1 VCORE 1 8 V VOS 1 0 01 8 2 25...

Page 66: ...1 Vcore 1 8 V VOS 1 0 01 32 2100 2700 MSI clock 65 kHZ Range3 Vcore 1 2 V VOS 1 0 11 0 065 18 5 72 MSI clock 524 kHZ 0 524 37 92 MSI clock 4 2 MHZ 4 2 180 273 Supply current in Sleep mode Flash switch...

Page 67: ...K 65 kHz TA 40 C to 25 C 18 21 TA 85 C 33 40 TA 105 C 60 78 MSI clock 131 kHz fHCLK 131 kHz TA 40 C to 25 C 36 41 TA 55 C 39 44 TA 85 C 50 58 TA 105 C 78 95 All peripherals OFF code executed from Flas...

Page 68: ...40 C to 25 C 18 6 21 TA 85 C 24 5 28 TA 105 C 35 42 MSI clock 131 kHz fHCLK 131 kHz Flash ON TA 40 C to 25 C 22 25 TA 55 C 23 5 26 TA 85 C 28 5 31 TA 105 C 39 45 TIM9 and USART1 enabled Flash ON VDD f...

Page 69: ...6 TA 85 C 4 35 10 TA 105 C 11 0 23 LCD ON static duty 2 TA 40 C to 25 C 1 65 6 TA 55 C 2 1 7 TA 85 C 4 7 12 TA 105 C 11 0 27 LCD ON 1 8 duty 3 TA 40 C to 25 C 2 5 10 TA 55 C 4 65 11 TA 85 C 7 25 16 T...

Page 70: ...ion results not tested in production unless otherwise specified 2 LCD enabled with external VLCD static duty division ratio 256 all pixels active no LCD connected 3 LCD enabled with external VLCD 1 8...

Page 71: ...TC enabled RTC clocked by LSI no independent watchdog TA 40 C to 25 C VDD 1 8 V 0 82 A TA 40 C to 25 C 1 15 1 9 TA 55 C 1 15 2 2 TA 85 C 1 65 4 TA 105 C 2 75 8 3 2 RTC clocked by LSE external quartz n...

Page 72: ...RE 1 2 V VOS 1 0 11 Low power sleep and run APB1 TIM2 14 3 12 1 9 5 12 1 A MHz fHCLK TIM3 13 8 11 7 9 2 11 7 TIM4 13 2 11 1 8 7 11 1 TIM5 17 7 14 9 11 8 14 9 TIM6 4 8 4 0 3 0 4 0 TIM7 4 7 3 9 3 0 3 9...

Page 73: ...6 6 2 4 9 6 2 GPIOF 7 7 6 3 5 0 6 3 GPIOG 8 4 7 0 5 4 7 0 GPIOH 1 8 1 3 1 1 1 3 CRC 0 8 0 6 0 4 0 6 FLASH 26 3 19 3 18 3 3 DMA1 19 0 16 0 12 8 16 0 DMA2 17 0 14 5 11 5 14 5 All enabled 261 206 184 18...

Page 74: ...tial IDD measurement between all peripherals OFF an one peripheral with clock enabled in the following conditions fHCLK 32 MHz range 1 fHCLK 16 MHz range 2 fHCLK 4 MHz range 3 fHCLK 64kHz Low power ru...

Page 75: ...r sleep mode fHCLK 262 kHz fHCLK 262 kHz Flash enabled 46 fHCLK 262 kHz Flash switched OFF 46 tWUSTOP Wakeup from Stop mode regulator in Run mode ULP bit 1 and FWU bit 1 fHCLK fMSI 4 2 MHz 8 2 Wakeup...

Page 76: ...VDD VDD V VHSEL OSC_IN input pin low level voltage VSS 0 3VDD tw HSEH tw HSEL OSC_IN high or low time 12 ns tr HSE tf HSE OSC_IN rise or fall time 20 Cin HSE OSC_IN input capacitance 2 6 pF 1 Guarante...

Page 77: ...al external components specified in Table 28 In the application the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distorti...

Page 78: ...stor 200 k C Recommended load capacitance versus equivalent serial resistance of the crystal RS 3 RS 30 20 pF IHSE HSE driving current VDD 3 3 V VIN VSS with 30 pF load 3 mA IDD HSE HSE oscillator pow...

Page 79: ...cy Table 29 LSE oscillator characteristics fLSE 32 768 kHz 1 1 Guaranteed by characterization results not tested in production Symbol Parameter Conditions Min Typ Max Unit fLSE Low speed external osci...

Page 80: ...capacitance Typically it is between 2 pF and 7 pF Caution To avoid exceeding the maximum value of CL1 and CL2 15 pF it is strongly recommended to use a resonator with a load capacitance CL 7 pF Never...

Page 81: ...f 16 1 5 ACCHSI 2 2 Guaranteed by characterization results not tested in production Accuracy of the factory calibrated HSI oscillator VDDA 3 0 V TA 25 C 1 3 3 Guaranteed by test in production 1 3 VDDA...

Page 82: ...MSI range 5 2 1 MSI range 6 4 2 ACCMSI Frequency error after factory calibration 0 5 DTEMP MSI 1 MSI oscillator frequency drift 0 C TA 105 C 3 DVOLT MSI 1 MSI oscillator frequency drift 1 65 V VDD 3 6...

Page 83: ...ange 5 2 MSI range 6 Voltage range 1 and 2 2 MSI range 3 Voltage range 3 3 fOVER MSI MSI oscillator frequency overshoot Any range to range 5 4 MHz Any range to range 6 6 1 This is a deviation for an i...

Page 84: ...L input clock 2 2 Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT 2 24 MHz PLL input clock duty cycle 45 55 fPL...

Page 85: ...Maximum current peak during the whole programming erase operation 1 5 2 5 mA Table 36 Flash memory and data EEPROM endurance and retention Symbol Parameter Conditions Value Unit Min 1 1 Guaranteed by...

Page 86: ...oblems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software It should be noted that good EMC performance is highly...

Page 87: ...ectrostatic discharge ESD Electrostatic discharges a positive then a negative pulse separated by 1 second are applied to the pins of each sample according to each pin combination The sample size depen...

Page 88: ...ation is executed on the device the device is stressed by injecting current into the I O pins programmed in floating input mode While current is injected into the I O pin one at a time the device is c...

Page 89: ...akage current 4 VSS VIN VDD I Os with LCD 50 nA VSS VIN VDD I Os with analog switches 50 VSS VIN VDD I Os with analog switches and LCD 50 VSS VIN VDD I Os with USB 250 VSS VIN VDD Standard I Os 50 FT...

Page 90: ...derived from tests performed under the conditions summarized in Table 13 All I Os are CMOS and TTL compliant Table 43 Output voltage characteristics Symbol Parameter Conditions Min Max Unit VOL 1 2 1...

Page 91: ...V to 3 6 V 2 MHz CL 50 pF VDD 1 65 V to 2 7 V 1 tf IO out tr IO out Output rise and fall time CL 50 pF VDD 2 7 V to 3 6 V 125 ns CL 50 pF VDD 1 65 V to 2 7 V 250 10 Fmax IO out Maximum frequency 3 CL...

Page 92: ...4 TF OUT Table 45 NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit VIL NRST 1 NRST input low level voltage 0 3 VDD V VIH NRST 1 NRST input high level voltage 0 7 VDD VOL NRST 1 N...

Page 93: ...ails on the input output ction characteristics output compare input capture external clock PWM output DL E 670 538 1567 9 LOWHU QWHUQDO UHVHW WHUQDO UHVHW FLUFXLW Table 46 TIMx 1 characteristics 1 TIM...

Page 94: ...MHz to achieve standard mode I C frequencies It must be at least 4 MHz to achieve fast mode I C frequencies It must be a multiple of 10 MHz to reach the 400 kHz maximum I C fast mode clock Unit Min M...

Page 95: ...d 0 7VDD Table 48 SCL frequency fPCLK1 32 MHz VDD VDD_I2C 3 3 V 1 2 1 RP External pull up resistance fSCL I2C speed 2 For speeds around 200 kHz the tolerance on the achieved speed is of 5 For other sp...

Page 96: ...e mode 30 70 tsu NSS NSS setup time Slave mode 4tHCLK ns th NSS NSS hold time Slave mode 2tHCLK tw SCKH 2 tw SCKL 2 SCK high and low time Master mode tSCK 2 5 tSCK 2 3 tsu MI 2 Data input setup time M...

Page 97: ...2 SPI timing diagram slave mode and CPHA 1 1 1 Measurement points are done at CMOS levels 0 3VDD and 0 7VDD DL F W DK EWhd D K KhdW hd W D K hd D E d Khd E Khd WK WK d E E h E E K K K K DL 6 QSXW 3 02...

Page 98: ...A 98 133 DocID026119 Rev 5 Figure 23 SPI timing diagram master mode 1 1 Measurement points are done at CMOS levels 0 3VDD and 0 7VDD AI 6 3 UTPUT 0 3 54054 3 054 0 3 3 54 4 3 54 3 0 0 4 54 33 INPUT T...

Page 99: ...vels VDD USB operating voltage 3 0 3 6 V VDI 2 2 Guaranteed by characterization results not tested in production Differential input sensitivity I USB_DP USB_DM 0 2 V VCM 2 Differential common mode ran...

Page 100: ...m for 256xFs is 8 MHz MHz fCK I2S clock frequency Master data 32 bits 64xFs MHz Slave data 32 bits 64xFs DCK I2S clock frequency duty cycle Slave receiver 48KHz 30 70 tr CK I2S clock rise time Capacit...

Page 101: ...s sent before the first byte Figure 26 I2 S master timing diagram Philips protocol 1 1 Guaranteed by characterization results not tested in production 2 LSB transmit receive of the previously transmit...

Page 102: ...4 Voltage range 3 4 Table 55 ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Power supply 1 8 3 6 V VREF Positive reference voltage 1 8 1 VDDA VREF Negative reference voltage VSS...

Page 103: ...ar trigger conversion latency fADC 16 MHz 156 219 ns 2 5 3 5 1 fADC tSTAB Power up time 3 5 s 1 The Vref input can be grounded if neither the ADC nor the DAC are used this allows to shut down an exter...

Page 104: ...ic distortion 70 65 ET Total unadjusted error 2 4 V VDDA 3 6 V 1 8 V VREF 2 4 V fADC 4 MHz RAIN 50 TA 40 to 105 C 4 6 5 LSB EO Offset error 2 4 EG Gain error 4 6 ED Differential linearity error 1 2 EL...

Page 105: ...n accuracy To remedy this fADC should be reduced DPSOH RI DQ DFWX DO WUDQVIHU FXUYH 7KH LGHDO WUDQVIHU FXUYH QG SRLQW FRUUHODWLRQ OLQH DL H 7 7RWDO XQDGMXVWHG UURU PD LPXP GHYLDWLRQ EHWZHHQ WKH DFWXDO...

Page 106: ...cles Conversion 12 cycles Iref 300 A 700 A MS36686V1 Table 57 Maximum source impedance RAIN max 1 Ts s RAIN max k Ts cycles fADC 16 MHz 2 Multiplexed channels Direct channels 2 4 V VDDA 3 6 V 1 8 V VD...

Page 107: ...on VDDA supply VDDA 3 3 V No load middle code 0x800 210 320 No load worst code 0xF1C 320 520 RL 2 Resistive load DAC output buffer ON 5 k CL 2 Capacitive load 50 pF RO Output impedance DAC output buff...

Page 108: ...r CL 50 pF RL 5 k DAC output buffer ON 12 30 LSB No RL CL 50 pF DAC output buffer OFF 8 12 tSETTLING Settling time full scale for a 12 bit code transition between the lowest and the highest input code...

Page 109: ...ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when buffer is OFF and from code giving 0 2 V and VDDA 0 2 V when buffer is ON 8 In buffered mode the output...

Page 110: ...20 CL Capacitive load 50 pF VOHSAT High saturation voltage Normal mode ILOAD max or RL min VDD 100 mV Low power mode VDD 50 VOLSAT Low saturation voltage Normal mode 100 Low power mode 50 m Phase marg...

Page 111: ..._Slope 1 Average slope 1 48 1 61 1 75 mV C V110 Voltage at 110 C 5 C 2 2 Measured at VDD 3 V 10 mV V110 ADC conversion result is stored in the TS_CAL2 byte 612 626 8 641 5 mV IDDA TEMP 3 Current consu...

Page 112: ...r 2 input voltage range 0 VDDA V tSTART Comparator startup time Fast mode 15 20 s Slow mode 20 25 td slow Propagation delay 2 in slow mode 2 The delay is characterized for 100 mV input step with 10 mV...

Page 113: ...rence voltage 6 3 4 VLCD7 LCD internal reference voltage 7 3 55 Cext VLCD external capacitance 0 1 2 F ILCD 1 1 LCD enabled with 3 V internal step up active 1 8 duty 1 4 bias division ratio 64 all pix...

Page 114: ...ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark 7 1 LQFP144 20...

Page 115: ...Typ Max A 1 600 0 0630 A1 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 170 0 220 0 270 0 0067 0 0087 0 0106 c 0 090 0 200 0 0035 0 0079 D 21 800 22 000 22 200 0 8583 0 8661...

Page 116: ...low profile quad flat package top view example 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in produ...

Page 117: ...00 pin low profile quad flat package mechanical data Symbol millimeters inches 1 Min Typ Max Min Typ Max A 1 600 0 0630 A1 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 170 0...

Page 118: ...ons are in millimeters E3 12 000 0 4724 e 0 500 0 0197 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 0 3 5 7 0 0 0 3 5 7 0 ccc 0 080 0 0031 1 Values in inches are converted from mm and...

Page 119: ...rked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will n...

Page 120: ...is not to scale Table 67 LQFP64 10 x 10 mm 64 pin low profile quad flat package mechanical data Symbol millimeters inches 1 Min Typ Max Min Typ Max A 1 600 0 0630 A1 0 050 0 150 0 0020 0 0059 A2 1 350...

Page 121: ...imensions are in millimeters E3 7 500 0 2953 e 0 500 0 0197 K 0 3 5 7 0 3 5 7 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 ccc 0 080 0 0031 1 Values in inches are converted from mm and rou...

Page 122: ...d as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not...

Page 123: ...ll grid array package mechanical data Symbol millimeters inches 1 Min Typ Max Min Typ Max A 0 460 0 530 0 600 0 0181 0 0209 0 0236 A1 0 050 0 080 0 110 0 0020 0 0031 0 0043 A2 0 400 0 450 0 500 0 0157...

Page 124: ...ee 0 150 0 0059 fff 0 050 0 0020 1 Values in inches are converted from mm and rounded to 4 decimal digits Table 68 UFBGA132 7 x 7 mm 132 ball ultra thin fine pitch ball grid array package mechanical d...

Page 125: ...1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such us...

Page 126: ...o scale Table 69 WLCSP64 0 400 mm pitch package mechanical data Symbol millimeters inches 1 Min Typ Max Min Typ Max A 0 540 0 570 0 600 0 0205 0 0224 0 0236 A1 0 190 0 0075 A2 0 380 0 0150 b 2 0 240 0...

Page 127: ...1 Values in inches are converted from mm and rounded to 4 decimal digits 2 Dimension is measured at the maximum bump diameter parallel to primary datum Z Table 70 WLCSP64 0 400 mm pitch package recomm...

Page 128: ...E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST...

Page 129: ...DD expressed in Watts This is the maximum chip internal power PI O max represents the maximum power dissipation on output pins where PI O max VOL IOL VDD VOH IOH taking into account the actual VOL IOL...

Page 130: ...ffix 6 Figure 47 Thermal resistance suffix 7 7 6 1 Reference document JESD51 2 Integrated Circuits Thermal Test Method Environment Conditions Natural Convection Still Air Available from www jedec org...

Page 131: ...it microcontroller Product type L Low power Device subfamily 151 Devices without LCD 152 Devices with LCD Pin count R 64 pins V 100 pins Z 144 pins Q 132 pins Flash memory size C 256 Kbytes of Flash m...

Page 132: ...ch ball grid array package recommended footprint 12 June 2014 3 Updated title removing memory I F Removed ambiguity of ambient temperature in the electrical characteristics description updated Figure...

Page 133: ...ledgement Purchasers are solely responsible for the choice selection and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products No license expre...

Page 134: ...ng Inventory Delivery Lifecycle Information STMicroelectronics STM32L151QCH6 STM32L151VCT6A STM32L152ZCT6 STM32L152QCH6 STM32L151ZCT6 STM32L151RCT6A STM32L152RCT6A STM32L152VCT6A STM32L151RCY6TR STM32...

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