DocID023833 Rev 5
7/36
STM32F42xx and STM32F43xx
ARM 32-bit Cortex-M4 with FPU limitations
35
1
ARM 32-bit Cortex-M4 with FPU limitations
An errata notice of the STM32F42xx and STM32F43xx core is available from the following
web address:
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b_errata_01/index.html.
All the described limitations are minor and related to the revision r0p1-v1 of the CortexM4
core.
summarizes these limitations and their implications on the behavior of
STM32F42xx and STM32F43xx devices.
1.1
Cortex-M4 interrupted loads to stack pointer can cause
erroneous behavior
Description
An interrupt occurring during the data-phase of a single word load to the stack pointer
(SP/R13) can cause an erroneous behavior of the device. In addition, returning from the
interrupt results in the load instruction being executed an additional time.
For all the instructions performing an update of the base register, the base register is
erroneously updated on each execution, resulting in the stack pointer being loaded from an
incorrect memory location.
The instructions affected by this limitation are the following:
•
LDR SP, [Rn],#imm
•
LDR SP, [Rn,#imm]!
•
LDR SP, [Rn,#imm]
•
LDR SP, [Rn]
•
LDR SP, [Rn,Rm]
Workaround
As of today, no compiler generates these particular instructions. This limitation can only
occur with hand-written assembly code.
Both limitations can be solved by replacing the direct load to the stack pointer by an
intermediate load to a general-purpose register followed by a move to the stack pointer.
Example:
Replace LDR SP, [R0] by
LDR R2,[R0]
MOV SP,R2
Table 3. Cortex-M4 core limitations and impact on microcontroller behavior
ARM ID
ARM
category
ARM summary of errata
Impact on STM32F42xx
and STM32F43xx
752419
Cat 2
Interrupted loads to SP can cause erroneous
behavior
Minor
