DocID018909 Rev 11
839/1731
RM0090
Inter-integrated circuit (I
2
C) interface
864
Figure 243. Transfer sequence diagram for master transmitter
1. The EV5, EV6, EV9, EV8_1 and EV8_2 events stretch SCL low until the end of the corresponding software
sequence.
2. The EV8 event stretches SCL low if the software sequence is not complete before the end of the next byte
transmission.
7-bit master transmitter
10-bit
master transmitter
Legend:
S
=
S
t
a
rt,
S
r
= Repe
a
ted
S
t
a
rt, P=
S
top, A= Acknowledge,
EVx= Event (with interr
u
pt if ITEVFEN = 1)
EV5:
S
B=1, cle
a
red by re
a
ding
S
R1 regi
s
ter followed by writing DR regi
s
ter with Addre
ss
.
EV6:
ADDR=1, cle
a
red by re
a
ding
S
R1 regi
s
ter followed by re
a
ding
S
R2.
EV8_1:
TxE=1,
s
hift regi
s
ter empty, d
a
t
a
regi
s
ter empty, write D
a
t
a
1 in DR.
EV8:
TxE=1,
s
hift regi
s
ter not empty, d
a
t
a
regi
s
ter empty, cle
a
red by writing DR regi
s
ter
.
EV8_2:
TxE=1, BTF = 1, Progr
a
m
S
top req
u
e
s
t. TxE
a
nd BTF
a
re cle
a
red by h
a
rdw
a
re by the
S
top condition
EV9:
ADD10=1, cle
a
red by re
a
ding
S
R1 regi
s
ter followed by writing DR regi
s
ter.
S
Addre
ss
A
D
a
t
a
1
A
D
a
t
a
2
A
.....
D
a
t
a
N
A
P
EV5
EV6
EV
8
_1
EV
8
EV
8
EV
8
EV
8
_2
S
He
a
der
A
Addre
ss
A
D
a
t
a
1
A
.....
D
a
t
a
N
A
P
EV5
EV9
EV6
EV
8
_1
EV
8
EV
8
EV
8
_2
a
i1
8
210