DocID018909 Rev 11
221/1731
RM0090
Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)
268
If the HSE oscillator is used directly or indirectly as the system clock (indirectly meaning that
it is directly used as PLL input clock, and that PLL clock is the system clock) and a failure is
detected, then the system clock switches to the HSI oscillator and the HSE oscillator is
disabled.
If the HSE oscillator clock was the clock source of PLL used as the system clock when the
failure occurred, PLL is also disabled. In this case, if the PLLI2S was enabled, it is also
disabled when the HSE fails.
7.2.8 RTC/AWU
clock
Once the RTCCLK clock source has been selected, the only possible way of modifying the
selection is to reset the power domain.
The RTCCLK clock source can be either the HSE 1 MHz (HSE divided by a programmable
prescaler), the LSE or the LSI clock. This is selected by programming the RTCSEL[1:0] bits
in the
RCC Backup domain control register (RCC_BDCR)
and the RTCPRE[4:0] bits in
clock configuration register (RCC_CFGR)
. This selection cannot be modified without
resetting the Backup domain.
If the LSE is selected as the RTC clock, the RTC will work normally if the backup or the
system supply disappears. If the LSI is selected as the AWU clock, the AWU state is not
guaranteed if the system supply disappears. If the HSE oscillator divided by a value
between 2 and 31 is used as the RTC clock, the RTC state is not guaranteed if the backup
or the system supply disappears.
The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not. As a
consequence:
•
If LSE is selected as the RTC clock:
–
The RTC continues to work even if the V
DD
supply is switched off, provided the
V
BAT
supply is maintained.
•
If LSI is selected as the Auto-wakeup unit (AWU) clock:
–
The AWU state is not guaranteed if the V
DD
supply is powered off. Refer to
Section 7.2.5: LSI clock on page 220
for more details on LSI calibration.
•
If the HSE clock is used as the RTC clock:
–
The RTC state is not guaranteed if the V
DD
supply is powered off or if the internal
voltage regulator is powered off (removing power from the 1.2 V domain).
Note:
To read the RTC calendar register when the APB1 clock frequency is less than seven times
the RTC clock frequency (f
APB1
< 7xf
RTCLCK
), the software must read the calendar time and
date registers twice. The data are correct if the second read access to RTC_TR gives the
same result than the first one. Otherwise a third read access must be performed.
7.2.9 Watchdog
clock
If the independent watchdog (IWDG) is started by either hardware option or software
access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator
temporization, the clock is provided to the IWDG.
