STMicroelectronics STM32F405, Reference Manual

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Flexible memory controller (FMC) RM0090
1596/1731 DocID018909 Rev 11
The application software uses the 3 sections to access the NAND Flash memory:
• To sending a command to NAND Flash memory , the software must write the
command value to any memory location in the command section.
•
To specify the NAND Flash address that must be read or written , the software
must write the address value to any memory location in the address section. Since an
address can be 4 or 5 byte long (depending on the actual memory size), several
consecutive write operations to the address section are required to specify the full
address.
• To read or write data, the software reads or writes the data from/to any memory
location in the data section.
Since the NAND Flash memory automatically increments addresses, there is no need to
increment the address of the data section to access consecutive memory locations.
37.4.3 SDRAM address mapping
The HADDR[28] bit (internal AHB address line 28) is used to select one of the two memory
banks as indicated in
Table 253 .
The following table shows SDRAM mapping for an 13-bit row ,a 11-bit column and 4 internal
bank configurations.
Table 252. NAND bank selection
Section name HADDR[17:16] Address range
Address section 1X 0x020000-0x03FFFF
Command section 01 0x010000-0x01FFFF
Data section 00 0x000000-0x0FFFF
Table 253. SDRAM bank selection
HADDR[28] Selected bank Control register Timing register
0 SDRAM Bank1 FMC_SDCR1 FMC_SDTR1
1 SDRAM Bank2 FMC_SDCR2 FMC_SDTR2
Table 254. SDRAM address mapping
Memory width
(1)
Internal bank Row address
Column
address
(2)
Maximum
memory capacity
(Mbyte)
8-bit HADDR[25:24] HADDR[23:11] HADDR[10:0]
64 Mbyte:
4 x 8K x 2K
16-bit HADDR[26:25] HADDR[24:12] HADDR[11:1]
128 Mbyte:
4 x 8K x 2K x 2
32-bit HADDR[27:26] HADDR[25:13] HADDR[12:2]
256 Mbyte:
4 x 8K x 2K x 4