DocID018909 Rev 11
RM0090
Flexible static memory controller (FSMC)
1588
Figure 448. Asynchronous wait during a write access
1. NWAIT polarity depends on WAITPOL bit setting in FSMC_BCRx register.
!;=
.7%
-EMORYTRANSACTION
.7!)4
$;=
.%X
DATADRIVENBY&3-#
AIC
(#,+
ADDRESSPHASE
DATASETUPPHASE
(#,+
DONTCARE
DONTCARE