DocID018909 Rev 11
155/1731
RM0090
Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)
212
The HSE Crystal can be switched on and off using the HSEON bit in the
6.2.2 HSI
clock
The HSI clock signal is generated from an internal 16 MHz RC oscillator and can be used
directly as a system clock, or used as PLL input.
The HSI RC oscillator has the advantage of providing a clock source at low cost (no external
components). It also has a faster startup time than the HSE crystal oscillator however, even
with calibration the frequency is less accurate than an external crystal oscillator or ceramic
resonator.
Calibration
RC oscillator frequencies can vary from one chip to another due to manufacturing process
variations, this is why each device is factory calibrated by ST for 1% accuracy at T
A
= 25 °C.
After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the
If the application is subject to voltage or temperature variations this may affect the RC
oscillator speed. You can trim the HSI frequency in the application using the HSITRIM[4:0]
bits in the
RCC clock control register (RCC_CR)
The HSIRDY flag in the
RCC clock control register (RCC_CR)
stable or not. At startup, the HSI RC output clock is not released until this bit is set by
hardware.
The HSI RC can be switched on and off using the HSION bit in the
The HSI signal can also be used as a backup source (Auxiliary clock) if the HSE crystal
oscillator fails. Refer to
Section 6.2.7: Clock security system (CSS) on page 157
6.2.3 PLL
configuration
The STM32F4xx devices feature three PLLs:
•
A main PLL (PLL) clocked by the HSE or HSI oscillator and featuring two different
output clocks:
–
The first output is used to generate the high speed system clock (up to 180 MHz)
–
The second output is used to generate the clock for the USB OTG FS (48 MHz),
the random analog generator (
≤
48 MHz) and the SDIO (
≤
48 MHz).
•
Two dedicated PLLs (PLLI2S and PLLSAI) used to generate an accurate clock to
achieve high-quality audio performance on the I2S and SAI1 interfaces.
PLLSAI is also
used for the LCD-TFT clock.
Since the main-PLL configuration parameters cannot be changed once PLL is enabled, it is
recommended to configure PLL before enabling it (selection of the HSI or HSE oscillator as
PLL clock source, and configuration of division factors M, N, P, and Q).
The PLLI2S and PLLSAI use the same input clock as PLL (PLLM[5:0] and PLLSRC bits are
common to both PLLs). However, the PLLI2S and PLLSAI have dedicated enable/disable
and division factors (N and R) configuration bits. Once the PLLI2S and PLLSAI are enabled,
the configuration parameters cannot be changed.
