STMicroelectronics STM32F405, Reference Manual

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RM0090 USB on-the-go full-speed (OTG_FS)
1368
34.16.1 CSR memory map
The host and device mode registers occupy different addresses. All registers are
implemented in the AHB clock domain.
Figure 395. CSR memory map
1. x = 3 in device mode and x = 7 in host mode.
Global CSR map
These registers are available in both host and device modes.
0000h
Core glob a l C S R s (1 Kbyte)
0400h
Ho s t mode C S R s (1 Kbyte)
0 8 00h
Device mode C S R s (1.5 Kbyte)
0E00h
Power a nd clock g a ting C S R s (0.5 Kbyte)
1000h
Device EP 0/Ho s t ch a nnel 0 FIFO (4 Kbyte)
2000h
Device EP1/Ho s t ch a nnel 1 FIFO (4 Kbyte)
3 000h
Device EP (x – 1)
(1)
/Ho s t ch a nnel (x – 1)
(1)
FIFO (4 Kbyte)
Device EP x
(1)
/Ho s t ch a nnel x
(1)
FIFO (4 Kbyte)
Re s erved
DFIFO
p
us h/pop
to thi s region
2 0000h
3 FFFFh
Direct a cce ss to d a t a FIFO RAM
for deb u gging (12 8 Kbyte)
DFIFO
deb
u g re a d/
write to thi s
region
a i15615b
Table 195. Core global control and status registers (CSRs)
Acronym
Address
offset
Register name
OTG_FS_GOTGCTL 0x000 OTG_FS control and status register (OTG_FS_GOTGCTL) on page 1262
OTG_FS_GOTGINT 0x004 OTG_FS interrupt register (OTG_FS_GOTGINT) on page 1264
OTG_FS_GAHBCFG 0x008 OTG_FS AHB configuration register (OTG_FS_GAHBCFG) on page 1265
OTG_FS_GUSBCFG 0x00C OTG_FS USB configuration register (OTG_FS_GUSBCFG) on page 1266
OTG_FS_GRSTCTL 0x010 OTG_FS reset register (OTG_FS_GRSTCTL) on page 1268