DocID026791 Rev 2
11/19
STEVAL-IME008V1
Schematic diagrams
19
Figure 10. STEVAL-IME008V1 circuit schematic (10 of 16)
SPI
EXTER
NAL PR
OGRAMMING HEADER
SPI FLASH CTRL SIGNALS
Place R38 close to the FPGA device
FPGA CONFIGURATION
Configuration mode selection:
FPGA_MODE0 = Parallel (Low) or Serial (High)
FPGA_MODE1 = Master (Low) or Slave (High)
TO CORRECT
EXT SPI
FLASH
Place D29
close to J10
C33 Details:
TDK (C2012X7R1A106K) - DIGIKEY (445-6857-2-ND)
Dimension 0805 - EIA 2012
When FPGA_INIT_B (bidirectional open-drain) is Low the configuration memory is
being cleared.
When held Low, the start of configuration is delayed.
During configuration, a Low on this output indicates that a configuration data
error has occurred.
CCLK
FPGA_SPI_MISO1
FPGA_SPI_MOSI
FPGA_SPI_SEL
FPGA_SPI_MISO2
FPGA_MODE0
FPGA_INIT_B
FPGA_MODE1
FPGA_SPI_MISO3
MCU_FPGA_INIT_B
MCU_FPGA_MODE1
+VFPGA_IO_3V3
+VFPGA_IO_3V3
FPGA_SPI_CCLK
FPGA_SPI_MISO1
FPGA_SPI_MOSI
FPGA_SPI_SEL
FPGA_SPI_MISO2
FPGA_SPI_MISO3
MCU_FPGA_PROG
D29
GREEN
R22
2K43 0402
56
R127
R38
33R2 0402
R21
R18
2K43 0402 DNP
J10
2K43 0402 DNP
CON10
10
1
2
3
4
5
6
7
8
9
C34
100nF
R17
2K43 0402
R16
10K 0402
R39
NA 0402
C33
10uF 10V 0805
R40
NA 0402
GSPG30072014DI1230
