Mains voltage
dips and interruptions
UM2027
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DocID029048 Rev 1
during the line interrupt. When the voltage is reapplied, the peak current is only 30 A as the
DC voltage only decreased by 60 V during the absence of AC voltage.
For case b, as the interrupt lasts more than 30 ms, the T_ICL Triac is re-triggered when the
AC voltage is reapplied. To avoid an excessive inrush current caused by long interrupts,
the T_ICL Triac is controlled in a soft-start procedure like for any system startup. The DC
capacitor thus starts being recharged when the T_ICL gate current is applied while the AC
voltage is higher than the C voltage. In
Figure 17: "(b) Board operation during 2-cycle line
interruption"
, this point occurs around 45 ms after the line voltage is reapplied. The peak
current is then only 10 A, which is only around two times the nominal current, comfortably
low enough to avoid any component damage.
Figure 16: "(a) Board operation during 1-cycle line interruption"
and
Figure 17: "(b) Board
operation during 2-cycle line interruption"
illustrate board operation during a 1-cycle (a) or
2-cycle (b) line interruption.
Figure 16: (a) Board operation during 1-
cycle line interruption
Figure 17: (b) Board operation during 2-
cycle line interruption
Table 4: "Required dips and interruptions tests and STEVAL-IHT008V1 performance"
lists
the different dips or interruption tests required for the different standards listed at the
beginning of this section. The test results of the STEVAL-IHT008V1 board are also given
for all tests.
These tests results only apply to the inrush current limitation function (thus T_ICL
Triac control).
Table 4: Required dips and interruptions tests and STEVAL-IHT008V1 performance
Standard
Application
Test type
%
residual
voltage
Number
of cycles
Required
criteria by
standard
STEVAL-
IHT008V1
result
IEC
61000-6-1
residential,
commercial and
light-industrial
environments
Dips
0
0.5
B
A
0
1
B
A
70
25
1
/30
2
C
A
Interruptions
0
250
1
/300
2
C
A
IEC
industrial
Dips
0
1
B
A
