Introduction
STCF03
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7.7 Acknowledge
The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock
pulse (see
). The peripheral (STCF03) that acknowledges has to pull-down (LOW)
the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during
this clock pulse. The peripheral which has been addressed has to generate an acknowledge
pulse after the reception of each byte, otherwise the SDA line remains at the HIGH level
during the ninth clock pulse duration. In this case the master transmitter can generate the
STOP information in order to abort the transfer. The STCF03 won't generate the
acknowledge if the V
I
supply is below the undervoltage lockout threshold.
7.8
Writing to a single register
Writing to a single register starts with a START bit followed by the 7 bit device address of
STCF03. The 8
th
bit is the R/W bit, which is 0 in this case. R/W = 1 means a reading
operation. Then the master waits for an acknowledge from STCF03. Then the 8 bit address
of register is sent to STCF03. It is also followed by an acknowledge pulse. The last
transmitted byte is the data that is going to be written to the register. It is again followed by
an acknowledge pulse from STCF03. Then master generates a STOP bit and the
communication is over. See
below.
Figure 7.
Acknowledge on I
2
C Bus
Table 8. Interface protocol
Device a R/W bit
Register address
Data
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
S
T
A
R
T
M
S
B
L
S
B
R
W
A
C
K
M
S
B
L
S
B
A
C
K
M
S
B
L
S
B
A
C
K
S
T
O
P
