STMicroelectronics SPEAr300, Reference Manual

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RS_Reconfigurable array subsystem (RAS) registers RM0082
658/844 Doc ID 018672 Rev 1
30.4.1 RAS Register 1 (0x99000000)
Due to limited number of GPIO pins available, they are shared between the IPs present in
fixed part and those present in RAS. This register implements the sharing of the PL_GPIO
pins between I/O alternate functions and the I/O functions of the RAS IPs.
If bit is '1', the I/Os alternate functions are connected to PL_GPIO pins.
If bit is '0', the IOs of corresponding RAS IP are connected to PL_GPIO pins.
0x5001_0000 0x5001_0FFF TDM Action memory AHB
0x5003_0000 0x5003_7FFF TDM Buffer memory AHB
0x5004_0000 0x5004_0FFF TDM Sync memory AHB
0x5005_0000 0x5005_0FFF I2S
I2S
memory bank 1 AHB
0x5005_1000 0x5005_1FFF I2S
I2S
memory bank 2 AHB
0x6000_0000 0x6FFF_FFFF CLCD AHB
0x7000_0000 0x7FFF_FFFF SDIO AHB
0x8000_0000 0x83FF_FFFF Static memory controller NAND Bank0 AHB
0x8400_0000 0x87FF_FFFF Static memory controller NAND Bank1 AHB
0x8800_0000 0x8BFF_FFFF Static memory controller NAND Bank2 AHB
0x8C00_0000 0x8FFF_FFFF Static memory controller NAND Bank3 AHB
0x9000_0000 0x90FF_FFFF Static memory controller Parallel NOR Bank0 AHB
0x9100_0000 0x91FF_FFFF Static memory controller Parallel NOR Bank1 AHB
0x9200_0000 0x92FF_FFFF Static memory controller Parallel NOR Bank2 AHB
0x9300_0000 0x93FF_FFFF Static memory controller Parallel NOR Bank3 AHB
0x9400_0000 0x98FF_FFFF Static memory controller Configuration Register AHB
0x9900_0000 0x9FFF_FFFF Registers AHB
0xA000_0000 0xA8FF_FFFF Keyboard APB
0xA900_0000 0xAFFF_FFFF GPIO APB
0xB000_0000 0xBFFF_FFFF - Reserved
Table 587. RAS memory map
Start address End address Peripheral Notes Bus
Table 588. RAS Register 1 description
Field
Default
Value
Description
[31:16] 16’h0 Reserved
[15] 1’h0
'0'- CLCD clock will be input to the RAS
'1'- Clock from Pll2/ClkR_Synt(3) will be output on PL_CLK1
[14] 1’h0 FIRDA
[13 1’h0 I2C