RM0082
HS_Media independent interface (MII)
Doc ID 018672 Rev 1
553/844
24.9
Clocks with MII
The clocking scheme for the MAC-AHB is shown in
. The MAC-AHB uses three
clock inputs for normal operation with the MII interface:
●
One clock (clk_tx_i) for transmission functions
●
One clock (clk_rx_i) for reception functions
●
One application clock (hclk_i)
All clocks except the Application clock are generated from an external PHY. The Application
clock is used for the control interface of the MAC-AHB. Transmit clock clk_tx_i is used for the
transmission function of the MAC-AHB. Similarly, receive clock clk_rx_i is used for the
receive function of the MAC-AHB. The transfer of data from/to the application clock domain
to the Transmit and Receive clock domains is performed in the MTL module.
Clock clk_tx_ i gets input from an external PHY (MII mode).
The external PHY outputs a 25 MHz or 2.5 MHz transmit clock on MII_CLK when it operates
at 100 Mbps or 10 Mbps, respectively. The frequency of clock clk_rx_i is same as receive
clock MII_RX_CLK generated by the external PHY. The PHY outputs a 25 MHz or 2.5 MHz
receive clock on MII_RX_CLK when it operates at 100 Mbps, or 10 Mbps, respectively.
[06]
1’h0
The bit is set when the rx128to255octects_gb counter
reaches half the maximum value.
[05]
1’h0
The bit is set when the rx65to127octects_gb counter
reaches half the maximum value.
[04]
1’h0
The bit is set when the rx64to127octects_gb counter
reaches half the maximum value.
[03]
1’h0
The bit is set when the rxmulticastframes_g counter
reaches half the maximum value.
[02]
1’h0
The bit is set when the rxbroadcastframes_g counter
reaches half the maximum value.
[01]
-
1’h0
RW
Setting this bit masks the interrupt when the
rxoctectcount_gb counter reaches half the maximum
value.
[00]
-
1’h0
RW
Setting this bit masks the interrupt when the
rxframecount_gb counter reaches half the maximum
value.
Table 466.
MMC receive interrupt mask register bit assignments (continued)
Bit
Name
Reset value Type
Description
