BS_General purpose timers
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Doc ID 018672 Rev 1
17.2.7 TIMER_COUNT
register
The TIMER_COUNT is a RO register indicates the current counter value. The
TIMER_COUNT bit assignments are given in
17.2.8 TIMER_REDG_CAPT
register
The TIMER_REDG_CAPT (timer rising edge capture) is a RO register which is used to
store the current value of the timer counter when a rising edge occurs. When a capture has
occurred, the REDGE bit is set in the TIMER_STATUS_INT_ACK register (
and the corresponding interrupt, if enabled (REDGE_INT bit set to 1‘b1 in
TIMER_CONTROL register,
), is raised.
The TIMER_REDG_CAPT bit assignments are given in
Note:
In the interrupt service routine, the capture register must be read before the next capture
event occurs: if not the current capture value will be overwritten by the next one.
17.2.9 TIMER_FEDG_CAPT
register
The TIMER_FEDG_CAPT (timer falling edge capture) is a RO register which is used to
store the current value of the counter when a falling edge occurs. When a capture has
occurred, the FEDGE bit is set in the TIMER_STATUS_INT_ACK register (
)
and the corresponding interrupt, if enabled (FEDGE_INT bit set to 1‘b1 in
TIMER_CONTROL register,
), is raised. The TIMER_FEDG_CAPT bit
assignments are given in
.
Note:
In the interrupt service routine, the capture register must be read before the next capture
event occurs: if not the current capture value will be overwritten by the next one.
Table 260.
TIMER_COUNT register bit assignments
Bit
Name
Reset value Description
[15:00]
CONT_VALUE
16’h0000
Current counter value.
Table 261.
TIMER_REDG_CAPT register bit assignments
Bit
Name
Reset
value
Description
[15:00]
COUNT_VALUE_REDGE 16’h0000
Current value of timer when a rising edge occurs
Table 262.
TIMER_FEDG_CAPT register bit assignments
Bit
Name
Reset
value
Description
[15:00]
CONT_VALUE_FEDGE
16’h0000
Current value of timer when a falling edge occurs