DDR memory controller (MPMC)
RM0082
130/844
Doc ID 018672 Rev 1
Let us consider System G as described in
. Again, to simplify the command queue is
considered to never be full, commands from ports 0, 1, 2 and 3 are only received at priority
level 0 and commands from ports 4 and 5 are always at priority 1.
However, now ports P0 - P1, and ports P4 - P5 are paired.
shows the system behavior with port pairing. Since ports P4 - P5 are still at a lower
priority, they will be ignored unless none of the higher priority ports (i.e. P0, P1, P2 or P3)
are requesting. Note the following points:
●
When either port of a port pair wins arbitration, the counters for both ports of the pair
increment.
●
In Cycle 3, the port pair P0/P1 reaches its allocated relative priority.
Note:
The port pair dynamically moves to the bottom of the scan order.
●
In Cycle 8, the port pair P4/P5 reaches its allocated relative priority. However, since
these are the only requests at priority 1, the scan order does not change.
Table 68.
System G specifications
Parameter
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
ahbX_priority0_relative_priority
3
3
2
2
1
1
ahbX_priority0_relative_priority
3
3
2
2
1
1
ahbX_priority0_relative_priority
3
3
2
2
1
1
weighted_round_robin_weight_sharing
1 (Paired)
0 (Not Paired)
1 (Paired)
Table 69.
System G operation
Cycle
Ports Requesting
Arbitration
Winner
Next Counter
Next Scan Order
P0 P1 P2 P3 P4 P5
P0 P1 P2 P3 P4 P5
Priority 0: P0-P1-P2-P3
Priority 1: P4-P5
0
Y
Y
P0
1
1
0
0
0
0
P0-P1-P2-P3
P5-P4
1
Y
Y
Y
P0
2
2
0
0
0
0
P0-P1-P2-P3
P5-P4
2
Y
Y
P2
2
2
1
0
0
0
P0-P1-P2-P3
P5-P4
3
Y
Y
Y
Y
P0
3
3
1
0
0
0
P2-P3-P0-P1
P5-P4
4
Y
Y
Y
P3
0
0
1
1
0
0
P2-P3-P0-P1
P5-P4
5
Y
Y
Y
P3
0
0
1
2
0
0
P2-P0-P1-P3
P5-P4
6
Y
Y
P1
1
1
1
0
0
0
P2-P0-P1-P3
P5-P4
