STMicroelectronics SPEAr300, Reference Manual

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RM0082 DDR memory controller (MPMC)
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10.4 Main block description
The multi-port memory controller supports high memory bandwidth utilization and an
efficient arbitration scheme for high priority agent requests.
The memory controller architecture consists of the following main sub-blocks:
●
AHB port interfaces.
● Arbiter.
●
Command queue with placement logic.
● Write data queue.
●
DRAM command processing.
The core controller interfaces with standard AHB ports through the interface blocks. All
requests are processed through the internal arbiter which feeds single commands to the
command queue of core controller. Write and read data is routed independently of the
arbiter through the data interfaces. There are multiple write data interfaces to the write data
queue of core controller, and a single read data interface back from the core controller to the
port interface blocks. The architecture of the multi-port system is shown in
Figure 8 .
Figure 8. Memory controller architecture
The interface blocks contain FIFOs for commands, READ and WRITE data, handling any
clock domain crossings as required. From the port interface blocks, commands are
processed by an Arbiter which feeds single commands to the command queue of the
Memory Controller core. WRITE and READ data are routed directly to the WRITE and
READ data queues of the Memory Controller core, Arbiter independently.
Each port has a distinct WRITE data interface to the WRITE data queue of the Memory
Controller core. However, for READ data, all ports share a single READ data interface back
to the port interface blocks.
AHB0
AHB1
AHB2
AHB3
AHB4
Placement
Logic
Port queue
Port queue
Port queue
Port queue
Port queue
Arbiter
Write data
queue
Command
queue
Read data
queue
CFG
REG
DRAM
Command
Logic
AHB-CFG
PHY
CORE Controller
AHB Port I/
F