Block diagram
UM1015
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Doc ID 18124 Rev 1
2 Block
diagram
Figure 2.
EVALSPEAr320CPU board block diagram
2.0.1
Dynamic memory subsystem
The Dynamic memory subsystem comprises three major parts:
Memory chip
The SPEAr320 MPU supports up to 256 Mbytes of memory. Place and route is provided for
2 chips but only one has been populated. The memory used is a Micron DDR2 device, its
part number is MT47H64M16HR-3 and its size is 128 Mbits x 8 (16 Mbits x 8 x 8 banks).
Local power supply
The local power supply is based on a monolithic voltage regulator for the chip set and
DDR2/3 (PM6641). It is generated locally in order to minimize the layout impact and also to
avoid any noise injection between different subsystems.
Signal termination
A parallel termination is added on the clock lines to compensate, if needed, for the layout
dissymmetry. Two 100k ohm resistors are used for each line in order to obtain an
impedance of 50 ohms. All the other terminations are directly inside the pads (both on the
SPEAr320 MPU and the memory sides).
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