Star Lake OXY5363A User Manual Download Page 1

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User’s Manual

Revision Date: Feb.14.2022

OXY5363A

3.5" SBC Form Factor Intel

Apollo Lake Processor

Summary of Contents for OXY5363A

Page 1: ...User s Manual Revision Date Feb 14 2022 OXY5363A 3 5 SBC Form Factor Intel Apollo Lake Processor ...

Page 2: ...ompany If the power supply is broken do not try to fix it by yourself Contact a qualified service technician or your local distributor Operation safety Before installing the motherboard and adding devices on it carefully read all the manuals that came with the package Before using the product make sure all cables are correctly connected and the power cables are not damaged If you detect any damage...

Page 3: ... ECC 2 x Intel I210 IT Giga LAN 4 x USB 3 0 1 x HDMI 1 4 1 x VGA 2 x RJ 45 Wide Temperature Optional 40 to 85 C OXY5323A 02ET Intel Apollo Lake M N3350 DDR3L 1866MHz 1 x 204 pin SO DIMM Max 8GB Non ECC 2 x Intel I210 IT Giga LAN 4 x USB 3 0 1 x HDMI 1 4 1 x VGA 2 x RJ 45 Normal Temperature 20 to 70 C OXY5323A 02UT Intel Apollo Lake M N3350 DDR3L 1866MHz x 204 pin SO DIMM Max 8GB Non ECC 2 x Intel ...

Page 4: ...er 1 Product Information 7 1 1 Block Diagram 7 1 2 Specifications 7 1 3 Board Placement 8 Chapter 2 JUMPER SETTING AND PIN DEFINITION 9 2 1 LVDS panel pin Header 9 2 2 eDP panel pin Header 9 2 3 Audio pin out define 12 2 4 LAN port 12 2 5 SATA 13 2 6 Super I O 13 2 7 Back Panel I O 13 2 8 USB 14 2 9 PCI Express Expansion Slots 15 2 10 Expansion Slots Layout 16 2 11 Front Panel 16 2 12 MiAPI featur...

Page 5: ...uirements 23 Chapter 3 BIOS Specification 23 3 1 Main Page 23 3 2 Advanced Page 26 3 2 1 INTEL I210 Gigabit Network Connection 00 22 4D 4D 00 01 30 3 2 2 NIC Configuration 32 3 2 3 INTEL I210 Gigabit Network Connection 00 22 4D 4D 00 02 34 3 2 4 NIC Configuration 36 3 3 Driver Health 37 3 3 1 INTEL PRO 1000 7 3 20 PCIe 38 3 4 Trusted Computing 40 3 5 Smart Settings 42 3 6 NCT6116D Super IO Configu...

Page 6: ...nual Revision Date Feb 14 2022 5 3 10 Platfrom Trust Technology 57 3 11 Chipset 59 3 12 Security 65 3 12 1 HDD Security Configuration 67 3 12 2 Secure Boot Mode 69 3 12 3 Key Managerment 71 3 13 Boot 76 3 14 Save Exit 80 ...

Page 7: ...OXY5323A User s Manual Revision Date Feb 14 2022 6 Chapter 1 Production Introduction 1 1Block Diagram ...

Page 8: ...s M 2 2230 E key PCIe USB BIOS AMI BIOS H W Monitor Temperature Monitor Voltage Monitor Watchdog Timer 1 to 255 Steps by Software Program Smart Fan Control CPU Fan Graphics VGA Up to 1920 x 1200 60 Hz HDMI Up to 4K 3840 x 2160 30 Hz LVDS Up to 1920 x 1200 60 Hz eDP Option Up to 4K 3840 x 2160 60 Hz Rear I O USB 4 x USB 3 0 Display I O 1 x HDMI 1 4 1 x VGA LAN I O 2 x RJ 45 Internal Connectors Stor...

Page 9: ... 1 x CMOS Jumper Power Requirement Power Input 8 24V Wide Range DC Input w 4 pin ATX connector Pitch 4 2mm Environmental Operating Temperature 20 to 70 C Optional 40 to 85 C Storage Temperature 40 to 85 C Operating Humidity 10 to 95 R H non condensing Standard Compliance Standard Compliance CE FCC OS OS Support Windows 10 64bit Linux Support by request ...

Page 10: ...OXY5323A User s Manual Revision Date Feb 14 2022 9 1 3 Board Placement ...

Page 11: ...gnal of odd channel 1 LVDS 9 Minus signal of odd channel 2 LVDS 10 Ground 11 Plus signal of odd channel 2 LVDS 12 Minus signal of odd channel 2 LVDS 13 Ground 14 Plus signal of odd channel 2 LVDS 15 Minus signal of odd clock channel LVDS 16 Minus signal of odd clock channel LVDS 17 Plus signal of odd clock channel LVDS 18 Plus signal of odd clock channel LVDS 19 Minus signal of odd channel 3 LVDS ...

Page 12: ...N DDPD_ 2 N 26 LCD_GND 7 Lane2_P DDPD_ 2 P 27 HDP DDPD_HPD 8 High speed_ GND 28 BKLT_GND 9 Lane1_N DDPD_ 1 N 29 BKLT_GND 10 Lane1_P DDPD_ 1 P 30 BKLT_GND 11 High speed_ GND 31 BKLT_GND 12 Lane0_N DDPD_ 0 N 32 BKLT_ENABLE 13 Lane0_P DDPD_ 0 P 33 BKLT_PWM_DIM 14 High speed_ GND 34 NC_ Reserved 15 AUX_CH_P DDPD_AUXP 35 NC_ Reserved 16 AUX_CH_N DDPD_AUXN 36 BKLT_PWR 17 High speed_ GND 37 BKLT_PWR 18 L...

Page 13: ...option 2 BKLT_PWR BKLT_PWR 3 12V 12V option default FPD_PWR1 Pin out define Pin Signal Description 1 BKLT_EN Backlight enable 2 BKLT_PWM Backlight control 3 BKLT_PWR Backlight inverter power 4 BKLT_PWR Backlight inverter power 5 BKLT_GND Brightness _GND Ground shared 6 BKLT_GND Brightness _GND Ground shared 7 Brightness _Up Panel brightness increase 8 Brightness _Down Panel brightness decrease 3 3...

Page 14: ...k Detect 7 F_IO_SEN Front I O Sensor 8 Key 9 FRO L Front Left 10 LINE2_JD LINE 2 Jack Detect 2 4 LAN port Diagram LED Color State Condition Link N A Off LAN link is not established Green On LAN link is established Blinking LAN activity occurring Speed N A Off 10 Mb s data rate Green On 100 Mb s data rate Yellow On 1000 Mb s data rate 1 2 4 6 10 3 5 7 9 FPAUDIO2 4 10 9 7 6 5 3 2 1 Port2L Sense _Sen...

Page 15: ...e compliant with the Serial ATA Revision 3 0 Specification as noted in the Reference Documentation section 2 6 Super I O Board must support the following featu Support for as one fan headers as required in section 1 4 2 Support minimum of 2 temperature inputs per PWM Controller for duty cycle determination Support for non ACPI based fan control thermal responsiveness independent of system Legacy I...

Page 16: ...y no pin 10 No Connect Rear USB3 0 I O port J5 J10 Pin Signal Name Description Mating Sequence J5 J10 1 VBUS Power Second 2 D USB 2 0 differential pair Third 3 D 4 GND Ground for power return Second 5 StdA _SSRX SuperSpeed receiver differential pair Last 6 StdA_ SSRX 7 GND_DRAIN Ground for signal return 8 StdA_ SSTX SuperSpeed transmitter differential pair 9 StdA_ SSTX Shell Shield Connector metal...

Page 17: ...with 25W requirement as defined in the PCI Express Card Electromechanical 3 0 Specification PCI Express x1 slot s must be compatible with x1 PCI Express add on cards Route WAKE to support ACPI wake events Design must provide SMBus routed to all PCI Express slots with individual per slot de stuffing option via strapping resistor strapping resistor must be stuffed by default Follow the ATX specifica...

Page 18: ... 2 11 Front Panel Pin out define JS2 Pin Signal Name Description Pin Signal Name Description 1 HDD_POWER_LED Pull up resistor 750Ώ to 5V 2 POWER_LED_MAIN Out Front panel LED main color 3 HDD_LED Out Hard disk activity LED 4 POWER_LED_ALT Out Front panel LED alt color 5 GROUND Ground 6 POWER_SWITCH In Power switch 7 RESET_SWITCH In Reset switch 8 GROUND Ground 9 5V_DC Power 10 KEY No pin PWR_LED ON...

Page 19: ...API_GPIO1 2 VCC 3 MAPI_GPIO2 4 MAPI_GPIO6 5 MAPI_GPIO3 6 MAPI_GPIO7 7 MAPI_GPIO4 8 MAPI_GPIO8 9 MAPI_GPIO5 10 MAPI_GPIO9 11 Watchdog Timer 12 MAPI_GPIO10 13 Power Button 14 SMB_MAIN_DATA 15 UART_TX 16 SMB_MAIN_CLK 17 UART_RX 18 5VSB 19 GND 20 N C 2 13 Serial Port J_RS485_P4 J_RS232_P2 Serial port header pin out define ...

Page 20: ...rier Detect 2 RXD Receive Data 3 TXD Transmit Data 4 DTR Data Terminal Ready 5 Ground 6 DSR Data Set Ready 7 RTS Request To Send 8 CTS Clear To Send 9 RI Ring Indicator 10 NC 11 DCD Data Carrier Detect 12 RXD Receive Data 13 TXD Transmit Data 14 DTR Data Terminal Ready 15 Ground 16 DSR Data Set Ready 17 RTS Request To Send 18 CTS Clear To Send 19 RI Ring Indicator 20 NC ...

Page 21: ...4 6 ATX 6 8 AT 5 7 PCIE 5 7 NA mSATA JUMPER 1 2 1 3 Clear CMOS Clear CMOS Normal JUMPER 8 6 4 6 AT ATX AT Mode ATX Default mSATA detection function JUMPER 5 7 IN 5 7 NA mSATA PCIE PCIE 3G Module Default mSATA 2 15 SATA power 1 25mm cable pin out define J_SATA_PWR1 Pin signal 1 5V 2 GND 3 NC J_SATA_PWR2 Pin signal 1 VCC3 2 GND 3 VCC 4 12V CMOS clear Normal 1 3 Clear CMOS 1 2 ...

Page 22: ...OXY5323A User s Manual Revision Date Feb 14 2022 21 2 16 ATX power 4P DC power 4 2mm pin out define J_PW4P_1 Pin signal 1 GND 2 GND 3 Power 8V 24V 4 Power 8V 24V ...

Page 23: ...SuperIO implementation must be supported by BIOS tools and drivers necessary for custom thermal profile management no later than by fab B samples BIOS tools driver support and subsystem validation is required The thermal management capability must support temperature sensors near CPU VR FETs as well as near or on the memory components shall only one temperature sensor be feasible it must be locate...

Page 24: ...OXY5323A User s Manual Revision Date Feb 14 2022 23 2 18 CPU Fans Processor fan header J20 ...

Page 25: ...ust be met for the 4 Closed loop fan speed control via the FANPWM0 signal routed to pin Locate closest to the CPU as required by the CDPG boxed CPU Chapter 3 BIOS Specification This chapter provides information about how to set up BIOS and use BIOS menu items to adjust basic function settings 3 1 MAIN PAGE ...

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Page 34: ...OXY5323A User s Manual Revision Date Feb 14 2022 33 3 2 2 NIC CONFIGURATION ...

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Page 36: ...OXY5323A User s Manual Revision Date Feb 14 2022 35 3 2 3 INTEL R I210 GIGABIT NETWORK CONNECTION 00 22 4D 4D 00 02 ...

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Page 38: ...OXY5323A User s Manual Revision Date Feb 14 2022 37 3 2 4 NIC CONFIGURATION ...

Page 39: ...OXY5323A User s Manual Revision Date Feb 14 2022 38 3 3DRIVER HEALTH ...

Page 40: ...OXY5323A User s Manual Revision Date Feb 14 2022 39 3 3 1 INTEL R PRO 1000 7 3 20 PCI E ...

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Page 42: ...OXY5323A User s Manual Revision Date Feb 14 2022 41 3 4 TRUSTED COMPUTING ...

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Page 44: ...OXY5323A User s Manual Revision Date Feb 14 2022 43 3 5 SMART SETTINGS ...

Page 45: ...OXY5323A User s Manual Revision Date Feb 14 2022 44 3 6 NCT6116D SUPER IO CONFIGURATION ...

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Page 48: ...OXY5323A User s Manual Revision Date Feb 14 2022 47 3 7 S5 RTC WAKE SETTINGS NO FUNCTION WHEN DEEPSX POWER POLICIES ENABLED ...

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Page 57: ...OXY5323A User s Manual Revision Date Feb 14 2022 56 3 9 NETWORK STACK CONFIGURATION ...

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Page 67: ...OXY5323A User s Manual Revision Date Feb 14 2022 66 3 12 SECURITY ...

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Page 69: ...OXY5323A User s Manual Revision Date Feb 14 2022 68 3 12 1 HDD SECURITY CONFIGURATION ...

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Page 82: ...OXY5323A User s Manual Revision Date Feb 14 2022 81 3 14 SAVE EXIT ...

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