Stanford Research Systems SR560, Manual

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CIRCUIT DESCRIPTION
14
adjustment is provided by this stage.
U405B, half of an AD7528 dual 8-bit DAC is
used to provide a ±5 volt offset voltage at
the non-inverting input of U402. The front
panel offset control also sums at this
junction, and provides an offset voltage of
±5 V that is buffered by U407D.
Following amplifier U402 is the other half of
the 8-bit DAC U405A, which along with op-
amp U404 forms a digital gain vernier. This
vernier is used in calibration to compensate
for gain variances that occur with
configuration changes such as input
coupling and filter settings. This DAC also
provides the front panel "uncal" gain vernier
function.
The sixth and final gain stage consists of
U403 and output buffer U406, configured for
a gain of 5 and with input attenuator U409
to select overall gains of 1, 2, or 5. The
LM6321, (U406) provides the output drive
capability for both the 600
Ω
and 50
Ω
outputs.
OVERLOAD DETECTION
The overload detector constantly monitors
the front-end output, filter 1 output, U402
(after the second filter) output, and final
stage output for excessive signal levels.
Comparator U408 compares both positive
and negative signal excursions against a 5
volt reference and lights the front panel
overload indicator if any levels are
excessive.
MICROPROCESSOR
The system processor U503 is a CMOS Z80
processor running at 4 MHz. The system
clock consists of Schmitt trigger U506A and
an R-C network. The oscillator is designed
so that latch U508A can shut down the
clock oscillator completely, thereby
disabling all digital circuits in the amplifier so
that no digital noise will be present. The
processor and clock only run when a front
panel key is pressed and instrument
settings are to be changed, or while there is
activity on the RS-232 port.
The SR560 uses a 16 K x 8 CMOS
EPROM, (U504) containing system
firmware and calibration bytes, along with a
2 K x 8 CMOS RAM, (U505) which is
battery backed-up at all times to retain
instrument settings.
U507 generates port strobes for system IO,
and U510 provides a buffered data bus.
The buffered data bus is active only during
IO instructions to keep digital noise in the
amplifier to a minimum while the processor
is running.
U601 through U606 are control latches
providing the 48 DC control lines that
configure all of the instrument's hardware.
U607 is an input buffer and takes data from
the front panel and RS-232, as well as
providing a processor input indicating line
operation and address from SW601 for
ganged RS-232 operation. SW601
additionally controls power to the front panel
LED’s through positions 3 and 4.
BATTERY CHARGER
AND PRE-REGULATORS
The 17 volt AC line transformer provides
unregulated power for both amplifier
operation and battery charging. Diode
bridge D706 and filter capacitors C706 and
C707 generate unregulated DC that is pre-
regulated to ±12 VDC by U706 and U707 to
take the place of the batteries when the
instrument is operating on AC line power.
Relay U705 switches the amplifier from
battery to pre-regulated AC whenever the
AC line cord is plugged in.
Diode bridge D710 and C709 and C710
provide unregulated DC to charge the
batteries. U701 and U702 operates as "AC"
regulators, limiting peak battery charging
voltage. As there are two positive batteries
and one negative battery, U701 is a LM350