1
Getting started
1.1
Overview
The
SIO and IO-Link device board, embedding the
intelligent dual channel IO-Link
transceiver, is designed to meet the electrical and communication protocol requirements with the IO-Link master.
The expansion board main features are:
•
IO-Link device dual transceiver in QFN package with the following main
characteristics:
–
2-channel (CQ and DIO) IO-Link PHY layer
–
IO-Link DLL (M-sequence handler and checksum)
–
Wake-up detection
–
Interrupt diagnostic pin
–
SPI and UART interfaces
–
50 mA 3.3 V and 5.0 V linear regulators
–
50 mA adjustable (5.0 ÷ 10.8 V) buck converter
–
Overload protection with adjustable intervention threshold
–
Overheating protection with adjustable shutdown threshold
–
Full reverse polarity on process side
–
Ground and V
CC
wire break protections
–
QFN-20L (4 x 4 x 0.9 mm) package
•
5 to 35 V operating voltage range
•
Red LED and green LED for status diagnostics
•
Radiated Emissions (EM Fields 30 MHz-1 GHz) < 40dB µV/m
•
Immunity to conducted disturbance (150 kHz-80 MHz) ≤ 10 V
•
Immunity to RF EM Fields (80 MHz-1 GHz) ≤ 10 V/m
•
Immunity to RF EM Fields (1 GHz-2.7 GHz) ≤ 3 V/m
•
Immunity to SURGE pulse (500 Ohm coupling) ≤ ± 1.2 kV
•
Immunity to ESD contact/air ≤ ±3 kV
•
Immunity to BURST noise ≤ ±1 kV
•
Compatible with
•
Equipped with Arduino UNO R3 connectors
•
RoHS and WEEE compliant
Important:
The
is designed for full compliance with EMC immunity levels required by IEC 61131-9 (and IEC 60947-5-2 for surge
expansion board, however, is intended for development purposes and the long net paths
along the Arduino connectors may impact ESD and Burst immunity levels.
1.1.1
Digital section
The digital section consists of the STM32 interface and the digital supply voltages to and from the
development board and the
expansion board via four Arduino UNO R3 connectors.
The on-board L1 inductor and C6 capacitor enable the step-down converter (active by default through SW4 by
closing 1-2) embedded in the
. The converter also supplies the two
internal LDOs to reduce
power dissipation, whose output voltage can supply the
development board via the V
in
net through
JP8 (closed) and CN6.
To supply your development board through an
LDO:
•
set JP5 to E5V for the
development board
•
close JP2 between pins 2-3 instead of 1-2 for the
The digital signal levels are set by the MCU on the
VDIG pin
is connected by SW2 to the proper voltage rail (3.3 V or 5.0 V from CN6).
UM2741
Getting started
UM2741
-
Rev 1
page 2/14