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uPSD3212A, uPSD3212C, uPSD3212CV

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Table 64. USB Interrupt Status Register (UISTA: 0E8h)

Table 65. Description of the UISTA Bits

7

6

5

4

3

2

1

0

SUSPND

—

RSTF

TXD0F

RXD0F

TXD1F

EOPF

RESUMF

Bit

Symbol

R/W

Function

7

SUSPND

R/W

USB Suspend Mode Flag.
To save power, this bit should be set if a 3ms constant idle state is
detected on USB bus. Setting this bit stops the clock to the USB and
causes the USB module to enter Suspend Mode. Software must clear
this bit after the Resume flag (RESUMF) is set while this Resume
Interrupt Flag is serviced

6

—

—

Reserved

5

RSTF

R

USB Reset Flag.
This bit is set when a valid RESET signal state is detected on the D+ and
D- lines. When the RSTE bit in the UIEN Register is set, this reset
detection will also generate an internal reset signal to reset the CPU and
other peripherals including the USB module.

4

TXD0F

R/W

Endpoint0 Data Transmit Flag.
This bit is set after the data stored in Endpoint 0 transmit buffers has
been sent and an ACK handshake packet from the host is received.
Once the next set of data is ready in the transmit buffers, software must
clear this flag. To enable the next data packet transmission, TX0E must
also be set. If TXD0F Bit is not cleared, a NAK handshake will be
returned in the next IN transactions. RESET clears this bit.

3

RXD0F

R/W

Endpoint0 Data Receive Flag.
This bit is set after the USB module has received a data packet and
responded with ACK handshake packet. Software must clear this flag
after all of the received data has been read. Software must also set
RX0E Bit to one to enable the next data packet reception. If RXD0F Bit is
not cleared, a NAK handshake will be returned in the next OUT
transaction. RESET clears this bit.

2

TXD1F

R/W

Endpoint1 / Endpoint2 Data Transmit Flag.
This bit is shared by Endpoints 1 and Endpoints 2. It is set after the data
stored in the shared Endpoint 1/ Endpoint 2 transmit buffer has been sent
and an ACK handshake packet from the host is received. Once the next
set of data is ready in the transmit buffers, software must clear this flag.
To enable the next data packet transmission, TX1E must also be set. If
TXD1F Bit is not cleared, a NAK handshake will be returned in the next
IN transaction. RESET clears this bit.

1

EOPF

R/W

End of Packet Flag.
This bit is set when a valid End of Packet sequence is detected on the D+
and D-line. Software must clear this flag. RESET clears this bit.

0

RESUMF

R/W

Resume Flag.
This bit is set when USB bus activity is detected while the SUSPND Bit is
set.
Software must clear this flag. RESET clears this bit.

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Summary of Contents for UPSD3212A

Page 1: ...d Low Voltage reset supervisor Programmable Watchdog Timer PROGRAMMABLE LOGIC GENERAL PURPOSE 16 macrocells Implements state machines glue logic and so forth COMMUNICATION INTERFACES I2 C Master Slave...

Page 2: ...37 No No 4 5 5 5 TQFP52 40 C to 85 C uPSD3212CV 24T6 24 64K 16K 2K 37 No No 3 0 3 6 TQFP52 40 C to 85 C uPSD3212C 40U6 40 64K 16K 2K 46 No Yes 4 5 5 5 TQFP80 40 C to 85 C uPSD3212CV 24U6 24 64K 16K 2K...

Page 3: ...fers 20 Boolean Instructions 23 Relative Offset 23 Jump Instructions 24 Machine Cycles 25 uPSD3200 HARDWARE DESCRIPTION 27 MCU MODULE DISCRIPTION 28 Special Function Registers 28 INTERRUPT SYSTEM 34 E...

Page 4: ...D SERIAL INTERFACE UART 55 Multiprocessor Communications 55 Serial Port Control Register 56 ANALOG TO DIGITAL CONVERTOR ADC 65 ADC Interrupt 65 PULSE WIDTH MODULATION PWM 67 4 channel PWM Unit PWM 0 3...

Page 5: ...AM Select 102 Page Register 105 PLDs 106 The Turbo Bit in PSD MODULE 106 Decode PLD DPLD 108 Complex PLD CPLD 109 Output Macrocell OMC 110 Product Term Allocator 111 Input Macrocells IMC 112 I O PORTS...

Page 6: ...TERFACE 127 Standard JTAG Signals 127 JTAG Extensions 127 Security and Flash memory Protection 127 INITIAL DELIVERY STATE 127 AC DC PARAMETERS 128 MAXIMUM RATING 130 EMC CHARACTERISTICS 131 Functional...

Page 7: ...dates in the field through In Application Programming IAP Dual Flash banks also support EEPROM emulation eliminat ing the need for external EEPROM chips General purpose programmable logic PLD is in cl...

Page 8: ...SCL1 29 P3 6 SDA1 28 P3 5 T1 27 P3 4 T0 PD1 CLKIN PC7 JTAG TDO JTAG TDI USB 1 PC4 TERR_ USB VCC GND PC3 TSTAT PC2 VSTBY JTAG TCK JTAG TMS 1 2 3 4 5 6 7 8 9 10 11 12 13 52 51 50 49 48 47 46 45 44 43 4...

Page 9: ...3 EXINT1 PD1 CLKIN ALE PC7 JTAG TDO JTAG TDI USB 1 PC4 TERR_ USB NC 2 VCC GND PC3 TSTAT PC2 VSTBY JTAG TCK NC 2 P4 7 PWM4 P4 6 PWM3 JTAG TMS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78...

Page 10: ...l 0 input P1 5 ADC1 60 I O General I O port pin ADC Channel 1 input P1 6 ADC2 61 I O General I O port pin ADC Channel 2 input P1 7 ADC3 64 I O General I O port pin ADC Channel 3 input A8 51 O External...

Page 11: ...input XTAL1 48 I Oscillator input pin for system clock XTAL2 49 O Oscillator output pin for system clock PA0 35 I O General I O port pin 1 PLD Macro cell outputs 2 PLD inputs 3 Latched Address Out A0...

Page 12: ...G pin 1 PLD Macro cell outputs 2 PLD inputs 3 SRAM stand by voltage in put VSTBY 4 SRAM battery on indicator PC4 5 JTAG pins are dedicated pins JTAG TCK 16 I JTAG pin PC2 VSTBY 15 I O General I O port...

Page 13: ...memory beyond the 64K bytes address space Refer to the PSD Module for details on mapping of the Flash memory The 8032 core has two types of data memory in ternal and external that can be read and writ...

Page 14: ...Flag CY This flag stores any carry or not borrow from the ALU of CPU after an arithmetic operation and is also changed by the Shift Instruc tion or Rotate Instruction Auxiliary Carry Flag AC After op...

Page 15: ...interval see Figure 10 Longer service routines can use a jump instruction to skip over subsequent interrupt locations if other interrupts are in use Data memory The internal data memory is divided int...

Page 16: ...ontains the address of the operand Both internal and ex ternal RAM can be indirectly addressed The ad dress register for 8 bit addresses can be R0 or R1 of the selected register bank or the Stack Poin...

Page 17: ...ons The arithmetic instructions is listed in Table 4 page 18 The table indicates the addressing modes that can be used with each instruction to access the byte operand For example the ADD A byte instr...

Page 18: ...he stack in the service routine The Rotate instructions RL A RLC A etc shift the Accumulator 1 bit to the left or right For a left rotation the MSB rolls into the LSB position For a right rotation the...

Page 19: ...te A A byte OR A X ORL byte data A byte OR data X XRL A byte A A XOR byte X X X X XRL byte A A byte XOR A X XRL byte data A byte XOR data X CRL A A 00h Accumulator only CPL A A NOT A Accumulator only...

Page 20: ...ved in the exchange To see how XCH and XCHD can be used to facilitate data manipulations consider first the problem of shifting and 8 digit BCD number two digits to the right Table 8 page 21 shows how...

Page 21: ...irect MOVs 14 bytes Table 8 Shifting a BCD Number Two Digits to the Right using direct XCHs 9 bytes Table 9 Shifting a BCD Number One Digit to the Right 2A 2B 2C 2D 2E ACC MOV A 2Eh 00 12 34 56 78 78...

Page 22: ...he desired table entry into the Accumula tor The other MOVC instruction works the same way except the Program Counter PC is used as the table base and the table is accessed through a subroutine First...

Page 23: ...the Exclusive OR of two bits C bit 1 XRL bit2 The software to do that could be as follows MOV C bit1 JNB bit2 OVER CPL C OVER continue First Bit 1 is moved to the Carry If bit2 0 then C now contains t...

Page 24: ...uction supports case jumps The destination address is computed at ex ecution time as the sum of the 16 bit DPTR regis ter and the Accumulator Typically DPTR is set up with the address of a jump table...

Page 25: ...irst is less than the second then the Carry Bit is set 1 If the first is greater than or equal to the second then the Carry Bit is cleared Machine Cycles A machine cycle consists of a sequence of six...

Page 26: ...5 S6 Read opcode Read next opcode S1 S2 S3 S4 S5 S6 Read next opcode and discard S1 S2 S3 S4 S5 S6 Read next opcode and discard Read next opcode and discard Read opcode MOVX Read next opcode S1 S2 S3...

Page 27: ...ough the internal address data bus A0 A15 D0 D7 and control signals RD_ WR_ PSEN_ ALE RESET_ The user defines the De coding PLD in the PSDsoft Development Tool and can map the resources in the PSD Mod...

Page 28: ...e not implement ed on the chip READ accesses to these addresses will in general return random data and WRITE accesses will have no effect User soft ware should write 0s to these unimplemented lo catio...

Page 29: ...1 91 P1SFS P1S7 P1S6 P1S5 P1S4 00 Port 1 Select Register 93 P3SFS P3S7 P3S6 00 Port 3 Select Register 94 P4SFS P4S7 P4S6 P4S5 P4S4 P4S3 P4S2 P4S1 P4S0 00 Port 4 Select Register 95 ASCL 00 8 bit Presca...

Page 30: ...L0H 00 Prescaler 0 High 8 bit B3 PSCL1L 00 Prescaler 1 Low 8 bit B4 PSCL1H 00 Prescaler 1 High 8 bit B7 IPA PS2 PI2C 00 Interrupt Priority 2nd B8 IP PT2 PS PT1 PX1 PT0 PX0 00 Interrupt Priority C0 P4...

Page 31: ...TXD0F RXD0F RXD1F EOPF RESUMF 00 USBInterrupt Status E9 UIEN SUSPNDIE RSTE RSTFIE TXD0IE RXD0IE TXD1IE EOPIE RESUMIE 00 USBInterrupt Enable EA UCON0 TSEQ0 STALL0 TX0E RX0E TP0SIZ3 TP0SiZ2 TP0SIZ1 TP0S...

Page 32: ...0 0A Input Macrocell Port A Reads latched value on Input Macrocells 0C Enable Out Port A Reads the status of the output enable control to the Port pin driver Bit 0 indicates pin is in input mode 01 Da...

Page 33: ...s protected C2 Secondary Flash Protection Security _Bit Sec1_ Prot Sec0_ Prot Security Bit 1 device is secured B0 PMMR0 PLD Mcells clk PLD array clk PLD Turbo APD enable 00 Control PLD power consumpti...

Page 34: ...hardware It is also generated by the T2EX signal Timer 2 External Interrupt P1 1 which is controlled by EXEN2 and EXF2 Bits in the T2CON register I2C Interrupt The interrupt of the I2 C is generated...

Page 35: ...12A uPSD3212C uPSD3212CV Figure 16 Interrupt System AI07427b INT0 USART Timer 0 I2C INT1 Timer 1 2nd USART Timer 2 High Low Interrupt Polling Interrupt Sources IE IP IPA Priority Global Enable USB www...

Page 36: ...f different pri ority occur simultaneously the high priority level request is serviced If requests of the same priority are received simultaneously an internal polling sequence determines which reques...

Page 37: ...ET1 Enable Timer 1 Interrupt 2 EX1 Enable External Interrupt Int1 1 ET0 Enable Timer 0 Interrupt 0 EX0 Enable External Interrupt Int0 Bit Symbol Function 7 Not used 6 Not used 5 Not used 4 ES2 Enable...

Page 38: ...inter rupt flag was once active but not serviced is not re membered Every polling cycle is new The processor acknowledges an interrupt request by executing a hardware generated LCALL to the appropria...

Page 39: ...reserved in its entirety Stack pointer Program counter Program status word Accumulator RAM and All other registers maintain their data during Idle Mode There are three ways to terminate the Idle Mode...

Page 40: ...h the alter native function is not used may be used as normal bi directional I O The use of Port1 Port4 pins as alternative func tions are carried out automatically by the uPSD321x Devices provided th...

Page 41: ...ons are con trolled using the P3SFS and P4SFS Special Func tion Selection registers After a reset the I O pins default to GPIO The alternate function is enabled if the corresponding bit in the PXSFS r...

Page 42: ...t input with internal pull up CMOS compatible interface NFC 400ns WR RD ALE PSEN O Output only XTAL1 XTAL2 I O On chip oscillator On chip feedback resistor Stop in the power down mode External clock i...

Page 43: ...l I O port with internal pull ups Schmitt input CMOS compatible interface Bidirectional I O port with internal pull ups Schmitt input TTL compatible interface PORT1 7 4 I O Bidirectional I O port with...

Page 44: ...biased to the transfer point Either a crystal or ce ramic resonator can be used as the feedback ele ment to complete the oscillator circuit Both are operated in parallel resonance XTAL1 is the high ga...

Page 45: ...g back up to the reset threshold the RESET signal will remain asserted for 10ms before it is released On initial power up the LVR is enabled default After power up the LVR can be disabled via the LVRE...

Page 46: ...les 1 258 seconds at 40MHz To reset the WDT the user must write a value between 00 7EH to the WDRST register The value that is written to the WDRST is loaded to the 7MSB of the 22 bit counter This all...

Page 47: ...WDT is enabled at power up or reset and must be served or disabled 7 6 5 4 3 2 1 0 Reserved WDRST6 WDRST5 WDRST4 WDRST3 WDRST2 WDRST1 WDRST0 Bit Symbol Function 7 Reserved 6 to 0 WDRST6 to WDRST0 To r...

Page 48: ...selection Timer 0 and Timer 1 have four operating modes from which to select Timer 0 and Timer 1 The Timer or Counter function is selected by control bits C T in the Special Function Register TMOD Th...

Page 49: ...o be reloaded into TL1 each time it overflows M1 M0 1 1 Timer Counter 1 stopped 4 M0 3 Gate Timer 0 Gating control when set Timer Counter 0 is enabled only while INT0 pin is High and TR0 control pin i...

Page 50: ...rements TR1 is a control bit in the Special Function Regis ter TCON TCON Control Register GATE is in TMOD The 13 bit register consists of all 8 bits of TH1 and the lower 5 bits of TL1 The upper 3 bits...

Page 51: ...causes the current value in the Timer 2 registers TL2 and TH2 to be captured into registers RCAP2L and RCAP2H respectively In addition the transition at T2EX causes Bit EXF2 in T2CON to be set and EXF...

Page 52: ...abled EXF2 1 will cause the CPU to vector to the Timer 2 Interrupt routine EXF2 must be cleared by software 5 RCLK 1 Receive Clock Flag UART 1 When set causes the serial port to use Timer 2 overflow p...

Page 53: ...Capture TR2 T2 pin Control TL2 8 bits TH2 8 bits C T2 0 C T2 1 12 EXP2 Control EXEN2 RCAP2L RCAP2H T2EX pin Timer 2 Interrupt Transition Detector AI06626 fOSC TF2 Reload TR2 T2 pin Control TL2 8 bits...

Page 54: ...now controls the Timer 1 In terrupt Mode 3 is provided for applications requiring an extra 8 bit timer on the counter With Timer 0 in Mode 3 an uPSD321x Devices can look like it has three Timer Counte...

Page 55: ...the Stop Bit is ignored The baud rate is pro grammable to either 1 32 or 1 64 the oscillator fre quency Mode 3 11 bits are transmitted through TxD or received through RxD a Start Bit 0 8 data bits LS...

Page 56: ...Serial Port In terrupt Bits TI and RI Figure 27 Serial Port Mode 0 Block Diagram Table 43 Serial Port Control Register SCON 7 6 5 4 3 2 1 0 SM0 SM1 SM2 REN TB8 RB8 TI RI AI06824 Zero Detector Internal...

Page 57: ...ables serial reception Set by software to enable reception Clear by software to disable reception 3 TB8 The 8th data bit that will be transmitted in Modes 2 and 3 Set or clear by software as desired 2...

Page 58: ...r configure UART 1 The RCLK1 and TCLK1 Bits in the PCON register configure UART 2 The Baud Rate Generator Mode is similar to the Auto reload Mode in that a roll over in TH2 causes the Timer 2 register...

Page 59: ...and all positions to the left of that contain zeros This condition flags the TX Control block to do one last shift and then deacti vate SEND and set T1 Both of these actions occur at S1P1 Both of the...

Page 60: ...purpose RxD is sampled at a rate of 16 times whatever baud rate has been es tablished When a transition is detected the di vide by 16 counter is immediately reset and 1FFH is written into the input sh...

Page 61: ...rial Port Interrupt Rx Clock Start Tx Clock Start Shift Shift Send Load SBUF TI RI CL D S Q 1FFh TxD Data Rx Detector RxD 1 to 0 Transition Detector 16 Sample 16 2 TB8 Timer1 Overflow Timer2 Overflow...

Page 62: ...out put position of the shift register then the Stop Bit is just to the left of TB8 and all positions to the left of that contain zeros This condition flags the TX Control unit to do one last shift a...

Page 63: ...erial Port Interrupt Rx Clock Start Tx Clock Start Shift Shift Send Load SBUF TI RI CL D S Q 1FFh TxD Data Rx Detector RxD 1 to 0 Transition Detector 16 Sample 16 2 TB8 Phase2 Clock 1 2 fOSC 0 1 SMOD...

Page 64: ...errupt Rx Clock Start Tx Clock Start Shift Shift Send Load SBUF TI RI CL D S Q 1FFh TxD Data Rx Detector RxD 1 to 0 Transition Detector 16 Sample 16 2 TB8 Timer1 Overflow Timer2 Overflow 0 0 1 1 0 1 T...

Page 65: ...the result is loaded into the ADAT the A D Conversion Status Bit ADSF is set to 1 The block diagram of the A D module is shown in Figure 35 The A D Status Bit ADSF is set auto matically when A D conv...

Page 66: ...ol Register Bit Symbol Function 7 to 6 Reserved 5 ADEN ADC Enable Bit 0 ADC shut off and consumes no operating current 1 enable ADC 4 Reserved 3 to 2 ADS1 ADS0 Analog channel select 0 0 0 1 1 0 1 1 Ch...

Page 67: ...han or equal to the counter value the corresponding PWM output is set LOW with PWML 0 The pulse width ratio is therefore de fined by the contents of the corresponding Special Function Register PWM 0 3...

Page 68: ...rs Registers 8 bit PWM0 PWM3 Comparators 8 8 8 bit Counter x 4 8 bit PWM0 PWM3 Data Registers 8 x 4 Port4 3 Port4 4 Port4 5 Port4 6 Overflow clock load 16 bit Prescaler Register B2h B1h 16 16 bit Pres...

Page 69: ...dr Reg Name Bit Register Name Reset Value Comment s 7 6 5 4 3 2 1 0 A1 PWMCON PWML PWMP PWME CFG4 CFG3 CFG2 CFG1 CFG0 00 PWM Control Polarity A2 PWM0 00 PWM0 Output Duty Cycle A3 PWM1 00 PWM1 Output D...

Page 70: ...eriod of the PWM The input clock to the Prescaler is fOSC 2 The PWM 4 channel is as signed to Port 4 7 Figure 37 Programmable PWM 4 Channel Block Diagram AI07091 Port 4 7 16 bit Prescaler Register B4h...

Page 71: ...es are loaded into the Comparator Registers and are compared to the Counter output When the content of the counter is equal to or greater than the value in the Pulse Width Register it sets the PWM 4 o...

Page 72: ...erates in 4 modes Master transmitter Master receiver Slave transmitter Slave receiver These functions are controlled by the SFRs see Tables 50 51 and Table 52 page 73 S2CON the control of byte handlin...

Page 73: ...STOP That is if this bit is set STOP condition in Master Mode is generated after 1 cycle interrupt period 3 ADDR This bit is set when address byte was received Must be cleared by software 2 AA Acknow...

Page 74: ...t Table 53 Serial Status Register S2STA Table 54 Description of the S2STA Bits Note 1 Interrupt Flag Bit INTR S2STA Bit 5 is cleared by Hardware as reading S2STA register 2 I2C Interrupt Flag INTR can...

Page 75: ...40MHz Table 59 System Clock Setup Examples 7 6 5 4 3 2 1 0 SLA6 SLA5 SLA4 SLA3 SLA2 SLA1 SLA0 Address Register Name Reset Value Note SFR D2h S2SETUP 00h To control the start stop hold time detection f...

Page 76: ...r and fre quency drift according to the USB specification The SIE also translates the electrical USB signals into bytes or signals Depending upon the device USB address and the USB endpoint Address th...

Page 77: ...Function 7 SUSPNDI R W Enable SUSPND Interrupt 6 RSTE R W Enable USB Reset also resets the CPU and PSD Modules when bit is set to 1 5 RSTFIE R W Enable RSTF USB Bus Reset Flag Interrupt 4 TXD0IE R W E...

Page 78: ...Bit is not cleared a NAK handshake will be returned in the next IN transactions RESET clears this bit 3 RXD0F R W Endpoint0 Data Receive Flag This bit is set after the USB module has received a data p...

Page 79: ...5 TX0E R W Endpoint0 Transmit Enable This bit enables a transmit to occur when the USB Host Controller sends an IN token to Endpoint 0 Software should set this bit when data is ready to be transmitte...

Page 80: ...except that the EP12SEL Bit is configured for Endpoint 1 the USB responds with a NAK handshake packet RESET clears this bit 5 TX1E R W Endpoint1 Endpoint2 Transmit Enable This bit enables a transmit t...

Page 81: ...his bit 0 STALL1 R W Endpoint1 Force Stall Bit RESET clears this bit 7 6 5 4 3 2 1 0 RSEQ SETUP IN OUT RP0SIZ3 RP0SIZ2 RP0SIZ1 RP0SIZ0 Bit Symbol R W Function 7 RSEQ R W Endpoint0 receive data packet...

Page 82: ...DT1 3 UDT1 2 UDT1 1 UDT1 0 00 USB Endpt1 Data Xmit E7 UDT0 UDT0 7 UDT0 6 UDT0 5 UDT0 4 UDT0 3 UDT0 2 UDT0 1 UDT0 0 00 USB Endpt0 Data Xmit E8 UISTA SUSPND RSTF TXD0F RXD0F RXD1F EOPF RESUMF 00 USB Int...

Page 83: ...operation The uPSD321x Devices driver tolerates a voltage on the signal pins of 0 5V to 3 6V with respect to local ground reference without damage The driver tolerates this voltage for 10 0 s while t...

Page 84: ...F IIO Data Line D D Leakage 0V D D 3 3 10 10 A RPU External Bus Pull up Resistance D 7 5k 2 to VCC 7 35 7 65 k RPD External Bus Pull down Resistance 15k 5 14 25 15 75 k Symb Parameter Test Conditions...

Page 85: ...Figure 41 The receiver tolerates static input voltages between 0 5V to 3 8V with respect to its local ground reference without damage In addition to the differential re ceiver there is a single ended...

Page 86: ...tive is defined for low speed devices with an inte grated cable The chip is specified for the 7 5k pull up This eliminates the need for an external 3 3V regulator or for a pin dedicated to providing...

Page 87: ...tter AI06633 Receiver EOP Width TEOPR1 TEOPR2 Differential Data Lines Source EOP Width TEOPT Crossover Point Crossover Point Extended Diff Data to SE0 Skew N TPERIOD TDEOP TPERIOD AI06634 Consecutive...

Page 88: ...16Kbit SRAM The SRAM s contents can be protected from a power failure by connecting an external battery CPLD with 16 Output Micro Cells OMCs and up to 20 Input Micro Cells IMCs The CPLD may be used t...

Page 89: ...CONTROL BUS PORT A B C 2 EXT CS TO PORT D 20 INPUT MACROCELLS PORT A B C 73 73 128KBIT SECONDARY NON VOLATILE MEMORY BOOT OR DATA 2 SECTORS 16KBIT BATTERY BACKUP SRAM RUNTIME CONTROL AND I O REGISTER...

Page 90: ...he same way by executing out of the primary Flash memo ry The PLD or other PSD MODULE Configuration blocks can be programmed through the JTAG port or a device programmer Table 80 indicates which progr...

Page 91: ...ro grammer may be purchased through your local distributor representative The uPSD3200 is also supported by third party device programmers See our web site for the current list Figure 47 PSDsoft Expre...

Page 92: ...res Port pin as input or output Drive Select 08 09 16 17 Configures Port pins as either CMOS or Open Drain on some pins while selecting high slew rate on other pins Input Macrocell 0A 0B 18 Reads Inpu...

Page 93: ...ry has a Select signal FS0 FS3 which can contain up to three product terms Each of the 2 sectors of the secondary Flash memory has a Se lect signal CSBOOT0 CSBOOT1 which can con tain up to three produ...

Page 94: ...mory Erase memory by chip or sector Suspend or resume sector erase Program a Byte RESET to READ Mode Read Sector Protection Status These instructions are detailed in Table 82 For ef ficient decoding o...

Page 95: ...14 Additional sectors to be erased must be written at the end of the Sector Erase instruction within 80 s 15 The data is 00h for an unprotected sector and 01h for a protected sector In the fourth cyc...

Page 96: ...protected or 00h if the sector is not protected The sector protection status for all NVM blocks primary Flash memory or secondary Flash mem ory can also be read by the MCU accessing the Flash Protecti...

Page 97: ...am Sector Erase or Bulk Erase cycle In the case of Flash memory programming the Er ror Flag Bit DQ5 indicates the attempt to program a Flash memory bit from the programmed state 0 to the erased state...

Page 98: ...Data Polling Flag Bit DQ7 and monitoring the Er ror Flag Bit DQ5 When the Data Polling Flag Bit DQ7 matches b7 of the original data and the Er ror Flag Bit DQ5 remains 0 the embedded algo rithm is co...

Page 99: ...simultaneously with the Error Flag Bit DQ5 see Figure 49 The Error Flag Bit DQ5 is set if either an internal time out occurred while the embedded algorithm attempted to program the byte or if the MCU...

Page 100: ...may be checked by reading the Error Flag Bit DQ5 the Toggle Flag Bit DQ6 and the Data Polling Flag Bit DQ7 as detailed in Programming Flash Memory page 98 During execution of the Erase cycle the Flas...

Page 101: ...n Status or Flash ID An Error condition has occurred and the device has set the Error Flag Bit DQ5 to 1 during a Flash memory Program or Erase cycle The Reset Flash instruction puts the Flash memo ry...

Page 102: ...e mapped in the same memory space as another Flash memory sector 3 A secondary Flash memory sector must not be mapped in the same memory space as another secondary Flash memory sector 4 SRAM I O and P...

Page 103: ...in the Program space at Boot up and later swap the primary and secondary Flash memories This is easily done with the VM Register by using PSDsoft Express Configuration to configure it for Boot up and...

Page 104: ...one memory space that allows the primary Flash memory sec ondary Flash memory and SRAM to be accessed by either Program Select Enable PSEN or READ Strobe RD For example to configure the prima ry Flash...

Page 105: ...ng is not needed or if not all 8 page register bits are needed for memory paging then these bits may be used in the CPLD for general logic Figure 53 shows the Page Register The eight flip flops in the...

Page 106: ...Dsoft The PLD input signals consist of internal MCU sig nals and external inputs from the I O ports The in put signals are shown in Table 87 The Turbo Bit in PSD MODULE The PLDs can minimize power con...

Page 107: ...ECONDARY NON VOLATILE MEMORY SELECTS DECODE PLD PAGE REGISTER PERIPHERAL SELECTS CPLD PT ALLOC MACROCELL ALLOC MCELLAB MCELLBC DIRECT MACROCELL ACCESS FROM MCU DATA BUS 20 INPUT MACROCELL PORT A B C 1...

Page 108: ...nal two product terms 1 internal CSIOP Select signal selects the PSD MODULE registers 2 internal Peripheral Select signals Peripheral I O Mode Figure 55 DPLD Logic Array Note 1 Port A inputs are not a...

Page 109: ...al data bus and can be directly accessed by the MCU This enables the MCU software to load data into the Output Macrocells OMC or read data from both the Input and Output Macrocells IMC and OMC This fe...

Page 110: ...th to the AND Array inputs The flip flop in the Output Macrocell OMC block can be configured as a D T JK or SR type in PS Dsoft The flip flop s clock preset and clear inputs may be driven from a produ...

Page 111: ...and Reading the Output Macrocells OMC The Output Macrocells OMC block oc cupies a memory location in the MCU address space as defined by the CSIOP block see I O PORTS PSD MODULE page 113 The flip flop...

Page 112: ...tput in the PSDabel file the port pin can be used for other I O functions The internal node feedback can be routed as an input to the AND Array Input Macrocells IMC The CPLD has 20 Input Macrocells IM...

Page 113: ...no longer available for other purposes Exceptions are not ed As shown in Figure 59 the ports contain an output multiplexer whose select signals are driven by the configuration bits in the Control Regi...

Page 114: ...be changed by writing to the corresponding bit in the Direction Register or by the output enable product term See Peripheral I O Mode page 114 When the pin is configured as an output the content of t...

Page 115: ...CU I O Yes Yes Yes Yes PLD I O McellAB Outputs McellBC Outputs Additional Ext CS Outputs PLD Inputs Yes No No Yes Yes Yes No Yes No Yes 3 No Yes No No Yes Yes Address Out Yes A7 0 Yes A7 0 No No Perip...

Page 116: ...e Direction Register has sole control of a given pin s direction An example of a configuration for a Port with the three least significant bits set to output and the re mainder set to input is shown i...

Page 117: ...acrocell OMC flip flop is blocked The default value is 0 or un blocked Input Macrocells IMC The Input Macrocells IMC can be used to latch or store external inputs The outputs of the Input Macrocells I...

Page 118: ...he Input Macrocells IMC Latched Address output Provide latched address output as per Table 91 page 115 Open Drain Slew Rate pins PA3 PA0 and PB3 PB0 can be configured to fast slew rate pins PA7 PA4 an...

Page 119: ...TAG programming Open Drain Port C pins can be configured in Open Drain Mode Battery Backup features PC2 can be configured for a battery input supply Voltage Standby VSTBY PC4 can be configured as a Ba...

Page 120: ...tions MCU I O Mode CPLD Output External Chip Select ECS1 ECS2 CPLD Input direct input to the CPLD no Input Macrocells IMC Slew rate pins can be set up for fast slew rate Port D pins can be configured...

Page 121: ...CS2 consists of one product term that can be configured active High or Low The output enable of the pin is controlled by either the output enable product term or the Direction Register See Figure 64 F...

Page 122: ...r down Mode if enabled Once in Power down Mode all address data signals are blocked from reaching memory and PLDs and the memories are deselected internally This allows the memory and PLDs to remain i...

Page 123: ...lso returns to normal Operating mode if either PSD Chip Select Input CSI PD2 is Low or the RESET input is High The MCU address data bus is blocked from all memory and PLDs Various signals can be block...

Page 124: ...put CSI PD2 disables the Flash memory and SRAM and reduces power consumption Howev er the PLD and I O signals remain operational when PSD Chip Select Input CSI PD2 is High Input Clock CLKIN PD1 can b...

Page 125: ...ted saving power Bit 3 PLD Array RD 0 on RD input to the PLD AND Array is connected 1 off RD input to PLD AND Array is disconnected saving power Bit 4 PLD Array PSEN 0 on PSEN input to the PLD AND Arr...

Page 126: ...Power on RESET Warm RESET and Power down Mode PLD outputs are always valid during Warm RESET and they are valid in Power on RESET once the internal Configuration bits are loaded This loading is comple...

Page 127: ...signals TMS TCK TDI and TDO They are used to speed Program and Erase cycles by indicating status on uPDS signals instead of having to scan the status out se rially using the standard JTAG channel See...

Page 128: ...power component gives the PLD Flash memory and SRAM mA MHz specification Figures 68 and 69 show the PLD mA MHz as a function of the number of Product Terms PT used In the PLD timing parameters add the...

Page 129: ...l product terms 45 182 24 7 Turbo Mode Off Calculation using typical values ICC total ICC MCUactive x MCUactive ICC PSDactive x PSDactive IPD pwrdown x pwrdown ICC MCUactive 20mA IPD pwrdown 250 A ICC...

Page 130: ...tions for extended periods may affect device reliability Refer also to the STMicroelectronics SURE Program and other relevant quality docu ments Table 105 Absolute Maximum Ratings Note 1 IPC JEDEC J S...

Page 131: ...am counter Unexpected reset Critical data corruption e g control registers Prequalification trials Most of the common fail ures unexpected reset and program counter cor ruption can be reproduced by ma...

Page 132: ...ode Power supplies are set to the typical values the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode This test conforms to the IEC 1000 4 2...

Page 133: ...ming Note Example tAVLX Time from Address Valid to ALE Invalid Table 112 AC Signal Behavior Symbols for Timing Note Example tAVLX Time from Address Valid to ALE Invalid Symbol Parameter Min Max Unit V...

Page 134: ...orms Key WAVEFORMS INPUTS OUTPUTS STEADY INPUT MAY CHANGE FROM HI TO LO MAY CHANGE FROM LO TO HI DON T CARE OUTPUTS ONLY STEADY OUTPUT WILL BE CHANGING FROM HI TO LO WILL BE CHANGING LO TO HI CHANGING...

Page 135: ...ipherals active 25 C operation 45 PLD product terms used PLD Turbo mode Off 24MHz MCU clock 12MHz PLD input frequency 25 12MHz MCU clock 1MHz PLD input frequency 7 mA Standby Current Typical Power dow...

Page 136: ...Low Voltage Ports 1 2 3 4 WR RD IOL 1 6mA 0 45 V VOL2 Output Low Voltage Port 0 ALE PSEN IOL 3 2mA 0 45 V VOH Output High Voltage Ports A B C D IOH 20 A VCC 4 5V 4 4 4 49 V IOH 2mA VCC 4 5V 2 4 3 9 V...

Page 137: ...input VCC 0V 0 5 1 A IIDLE SRAM PSD Idle Current VSTBY input VCC VSTBY 0 1 0 1 A IRST Reset Pin Pull up Current RESET VIN VSS 10 55 A IFR XTAL Feedback Resistor Current XTAL1 XTAL1 VCC XTAL2 VSS 20 5...

Page 138: ...VCC 3 0V 0 15 0 45 V VOL1 Output Low Voltage Ports 1 2 3 4 WR RD IOL 1 6mA 0 45 V IOL 100 A 0 3 V VOL2 Output Low Voltage Port 0 ALE PSEN IOL 3 2mA 0 45 V IOL 200 A 0 3 V VOH Output High Voltage Ports...

Page 139: ...V 2 5V for Port 4 pin 2 25 250 A ISTBY SRAM PSD Standby Current VSTBY input VCC 0V 0 5 1 A IIDLE SRAM PSD Idle Current VSTBY input VCC VSTBY 0 1 0 1 A IRST Reset Pin Pull up Current RESET VIN VSS 10 5...

Page 140: ...CLCL 24 to 40MHz Unit Min Max Min Max tLHLL ALE pulse width 35 2tCLCL 15 ns tAVLL Address set up to ALE 10 tCLCL 15 ns tLLAX Address hold after ALE 10 tCLCL 15 ns tLLIV ALE Low to valid instruction in...

Page 141: ...damage to Port 0 drivers Symbol Parameter 1 24MHz Oscillator Variable Oscillator 1 tCLCL 8 to 24MHz Unit Min Max Min Max tLHLL ALE pulse width 43 2tCLCL 40 ns tAVLL Address set up to ALE 17 tCLCL 25...

Page 142: ...vices and 50pF for 3V devices Symbol Parameter 1 40MHz Oscillator Variable Oscillator 1 tCLCL 24 to 40MHz Unit Min Max Min Max tRLRH Oscillator period 25 41 7 ns tWLWH High time 10 tCLCL tCLCX ns tLLA...

Page 143: ...to valid data in 75 5tCLCL 50 ns tRHDX Data hold after RD 0 0 ns tRHDZ Data float after RD 38 2tCLCL 12 ns tLLDV ALE to valid data in 150 8tCLCL 50 ns tAVDV Address to valid data in 150 9tCLCL 75 ns...

Page 144: ...D 63 2tCLCL 20 ns tLLDV ALE to valid data in 200 8tCLCL 133 ns tAVDV Address to valid data in 220 9tCLCL 155 ns tLLWL ALE to WR or RD 75 175 3tCLCL 50 tCLCL 50 ns tAVWL Address valid to WR or RD 67 4t...

Page 145: ...package only Symbol Parameter Conditions Min Max PT Aloc Turbo Off Slew rate 1 Unit tPD 2 CPLD Input Pin Feedback to CPLD Combinatorial Output 20 2 10 2 ns tEA CPLD Input to CPLD Output Enable 21 10...

Page 146: ...Off Slew rate 1 Unit fMAX Maximum Frequency External Feedback 1 tS tCO 40 0 MHz Maximum Frequency Internal Feedback fCNT 1 tS tCO 10 66 6 MHz Maximum Frequency Pipelined Data 1 tCH tCL 83 3 MHz tS Inp...

Page 147: ...Slew rate 1 Unit fMAX Maximum Frequency External Feedback 1 tS tCO 22 2 MHz Maximum Frequency Internal Feedback fCNT 1 tS tCO 10 28 5 MHz Maximum Frequency Pipelined Data 1 tCH tCL 40 0 MHz tS Input S...

Page 148: ...Input High Time 9 10 ns tCLA Clock Input Low Time 9 10 ns tCOA Clock to Output Delay 21 10 2 ns tARDA CPLD Array Delay Any macrocell 11 2 ns tMINA Minimum Clock Period 1 fCNTA 16 ns Symbol Parameter...

Page 149: ...r to tAVLX and tLXAX Symbol Parameter Conditions Min Max PT Aloc Turbo Off Unit tIS Input Setup Time Note 1 0 ns tIH Input Hold Time Note 1 15 10 ns tINH NIB Input High Time Note 1 9 ns tINL NIB Input...

Page 150: ...3 30 s Flash Bulk Erase not pre programmed 5 s tWHQV3 Sector Erase pre programmed 1 30 s tWHQV2 Sector Erase not pre programmed 2 2 s tWHQV1 Byte Program 14 150 s Program Erase Cycles per Sector 100 0...

Page 151: ...s Min Max Turbo Off Unit tAVQV PA Address Valid to Data Valid Note 1 37 10 ns tSLQV PA CSI Valid to Data Valid 27 10 ns tRLQV PA RD to Data Valid Note 2 32 ns tDVQV PA Data In to Data Out Valid 22 ns...

Page 152: ...a on Port A Symbol Parameter Conditions Min Max Unit tWLQV PA WR to Data Propagation Delay 25 ns tDVQV PA Data to Port A Data Propagation Delay Note 1 22 ns tWHQZ PA WR Invalid to Port A Tri state 20...

Page 153: ...Max Unit tNLNH RESET Active Low Time 1 150 ns tNLNH PO Power on Reset Active Low Time 1 ms tOPR RESET High to Operational Device 120 ns Symbol Parameter Conditions Min Max Unit tNLNH RESET Active Low...

Page 154: ...ck TCK PC1 Low Time except for PLD Note 1 23 ns tISCCFP Clock TCK PC1 Frequency PLD only Note 2 2 MHz tISCCHP Clock TCK PC1 High Time PLD only Note 2 240 ns tISCCLP Clock TCK PC1 Low Time PLD only Not...

Page 155: ...d VOH or VOL level occurs IOL and IOH 20mA Symbol Parameter Conditions Min Max Unit tISCCF Clock TCK PC1 Frequency except for PLD Note 1 12 MHz tISCCH Clock TCK PC1 High Time except for PLD Note 1 40...

Page 156: ...consult the crystal manufacturer for appropriate values of external components Figure 87 PSD MODULE AC Measurement I O Waveform Figure 88 PSD MODULEAC Measurement Load Circuit Table 143 Capacitance No...

Page 157: ...uPSD3212C uPSD3212CV PACKAGE MECHANICAL INFORMATION Figure 89 TQFP52 52 lead Plastic Thin Quad Flat Package Outline Note Drawing is not to scale QFP A Nd E1 CP b e A2 A N L A1 D1 D 1 E Ne c D2 E2 L1...

Page 158: ...ches Typ Min Max Typ Min Max A 1 75 0 069 A1 0 05 0 020 0 002 0 008 A2 1 25 1 55 0 049 0 061 b 0 02 0 04 0 007 0 016 c 0 07 0 23 0 002 0 009 D 12 00 0 473 D1 10 00 0 394 D2 E 12 00 0 473 E1 10 00 0 39...

Page 159: ...59 163 uPSD3212A uPSD3212C uPSD3212CV Figure 90 TQFP80 80 lead Plastic Thin Quad Flat Package Outline Note Drawing is not to scale QFP A Nd E1 CP b e A2 A N L A1 D1 D 1 E Ne c D2 E2 L1 www BDTIC com S...

Page 160: ...1 60 0 063 A1 0 05 0 15 0 002 0 006 A2 1 40 1 35 1 45 0 055 0 053 0 057 b 0 22 0 17 0 27 0 009 0 007 0 011 c 0 09 0 20 0 004 0 008 D 14 00 0 551 D1 12 00 0 472 D2 9 50 0 374 E 14 00 0 551 E1 12 00 0 4...

Page 161: ...SD Microcontroller PSD Family 3 8032 core PLD Size 2 16 Macrocells SRAM Size 1 2K bytes Main Flash Memory Size 2 64K bytes IP Mix A USB I2 C PWM ADC 2 UARTs Supervisor Reset Out Reset In LVD WD C I2C...

Page 162: ...lectrical characteristics Table 114 115 131 132 02 Sep 03 1 2 Update references for Product Catalog 03 Feb 04 2 0 Reformatted correct package dimensions Table 145 02 July 04 3 0 Reformatted add EMC ch...

Page 163: ...ce This publication supersedes and replaces all information previously supplied STMicroelectronics products are not authorized for use as critical components in life support devices or systems without...

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