RM0453 Rev 2
RM0453
Tamper and backup registers (TAMP)
1049
Trigger output generation on tamper event
The tamper event detection can be used as trigger input by the low-power timers.
When TAMPxMSK bit in cleared in TAMP_CR register, the TAMPxF flag must be cleared by
software in order to allow a new tamper detection on the same pin.
When TAMPxMSK bit is set, the TAMPxF flag is masked, and kept cleared in TAMP_SR
register. This configuration allows the low-power timers in Stop mode to be trigged
automatically, without requiring the system wakeup to perform the TAMPxF clearing. In this
case, the backup registers are not cleared.
This feature is available only when the tamper is configured in the
filtering on tamper inputs (passive mode)
mode.
Timestamp on tamper event
With TAMPTS set to 1 in the RTC_CR, any tamper event causes a timestamp to occur. In
this case, either the TSF bit or the TSOVF bit is set in RTC_SR, in the same manner as if a
normal timestamp event occurs. The affected tamper flag register TAMPxF is set in the
TAMP_SR at the same time that TSF or TSOVF is set in the RTC_SR.
Edge detection on tamper inputs (passive mode)
If the TAMPFLT bits are 00, the TAMP_INx pins generate tamper detection events when
either a rising edge/high level or a falling edge/low level is observed depending on the
corresponding TAMPxTRG bit. The internal pull-up resistors on the TAMP_INx inputs are
deactivated when edge detection is selected.
Caution:
When using the edge detection, it is recommended to check by software the tamper pin
level just after enabling the tamper detection (by reading the GPIO registers), and before
writing sensitive values in the backup registers, to ensure that an active edge did not occur
before enabling the tamper event detection.
When TAMPFLT = 00 and TAMPxTRG = 0 (rising edge detection), a tamper event may be
detected by hardware if the tamper input is already at high level before enabling the tamper
detection.
After a tamper event has been detected and cleared, the TAMP_INx should be disabled and
then re-enabled (TAMPxE set to 1) before re-programming the backup registers
(TAMP_BKPxR). This prevents the application from writing to the backup registers while the
TAMP_INx input value still indicates a tamper detection. This is equivalent to a level
detection on the TAMP_INx input.
Note:
Tamper detection is still active when V
DD
power is switched off. To avoid unwanted resetting
of the backup registers, the pin to which the TAMPx is mapped should be externally tied to
the correct level.
Level detection with filtering on tamper inputs (passive mode)
Level detection with filtering is performed by setting TAMPFLT to a non-zero value. A tamper
detection event is generated when either 2, 4, or 8 (depending on TAMPFLT) consecutive
samples are observed at the level designated by the TAMPxTRG bits.
The TAMP_INx inputs are precharged through the I/O internal pull-up resistance before its
state is sampled, unless disabled by setting TAMPPUDIS to 1. The duration of the
precharge is determined by the TAMPPRCH bits, allowing for larger capacitances on the
TAMP_INx inputs.